Memory device with independent plate line control
A memory device can include an array of memory cells comprising groups of memory cells, the groups including at least one redundant group for repairing a defective group. The memory device can include a controller coupled to the array. Responsive to receiving a memory access command, the controller can detect whether a defective group is present. If a defect is present, sensing operations are not performed for the defective group. If no defect is present, sensing operations are not performed for the redundant group.
1 . A memory device comprising:
an array of memory cells comprising a plurality of groups of memory cells, the plurality of groups including at least one redundant group for repairing a defective group, and each group is coupled to a respective independently-controlled plate line; and
a controller coupled to the array, wherein the controller is configured to:
responsive to receiving a memory access command, detect whether a defective group is present in the plurality of groups;
when a defective group is detected in the plurality of groups, inhibit sensing operations for the defective group; and
when a defective group is not detected in the plurality of groups, inhibit sensing operations for the redundant group;
wherein the sensing operations include powering respective plate lines for the respective groups.
2 . The memory device of claim 1 , wherein the sensing operations include ramping up power to a respective plate line coupled to each respective group and providing a biasing voltage to a respective second access line for each respective group.
3 . The memory device of claim 1 , wherein the controller is configured to provide a time delay upon receiving the memory access command and before initiating sensing operations.
4 . The memory device of claim 1 , wherein the controller is configured to mask the defective group upon receiving a read command or a write command.
5 . The memory device of claim 1 , wherein the controller is configured to mask the redundant group upon receiving a read command or a write command when no defect is detected within the plurality of groups.
6 . The memory device of claim 1 , wherein the array comprises ferroelectric RAM (FeRAM).
7 . The memory device of claim 2 , wherein the groups comprise column groups and wherein each of the plurality of groups is each coupled to a separate plate line.
8 . The memory device of claim 3 , wherein the controller is configured to load redundancy information to sense amplifier and plate control circuitry during the time delay.
9 . A method for accessing memory, the method comprising:
receiving a memory access command to access groups within an array of memory, the groups including at least one redundant group;
detecting whether a defective group is present within the groups;
when a defective group is detected, inhibit sensing operations for the defective group;
when a defective group is not detected, inhibit sensing operations for the at least one redundant group;
wherein the sensing operations include providing power to respective plate lines for each of the respective groups.
10 . The method of claim 9 , wherein the sensing operations include ramping up power to a respective plate line coupled to each respective group and providing a biasing voltage to a respective second access line for each respective group.
11 . The method of claim 9 , comprising providing a time delay upon receiving the memory access command and before initiating sensing operations.
12 . The method of claim 9 , comprising masking the defective group upon receiving a read command or a write command.
13 . The method of claim 11 , comprising loading redundancy information to read circuitry during the time delay.
14 . The method of claim 9 , comprising masking the redundant group upon receiving a read command or a write command if no defect is present within the array.
15 . A system comprising:
a host device; and
a memory device coupled to the host device, the memory device comprising:
an array of memory cells comprising a plurality of groups of memory cells, the plurality of groups including at least one redundant group for repairing a defective group, and each group is coupled to a respective independently-controlled plate line; and
a controller coupled to the array and configured to:
responsive to a memory access command, detect whether a defective group is present in the plurality of groups;
when a defective group is detected in the plurality of groups, inhibit sensing operations for the defective group; and
when a defective group is not detected in the plurality of groups, inhibit sensing operations for the redundant group;
wherein the sensing operations include powering respective plate lines for the respective groups.
16 . The system of claim 15 , wherein the sensing operations include ramping up power to a respective plate line coupled to each respective group and providing a biasing voltage to a respective second access line for each respective group.
17 . The system of claim 15 , wherein the controller is configured to provide a time delay upon receiving the memory access command and before initiating sensing operations.
18 . The system of claim 15 , wherein the memory device includes a ferroelectric random access memory (FeRAM) device.
19 . The system of claim 16 , wherein the groups comprise column groups and wherein each of the plurality of groups are each coupled to a separate plate line.
20 . The system of claim 17 , wherein the controller is configured to load redundancy information to read circuitry during the time delay.