Real time ramp rate adjustment for better performance and current consumption tradeoff
A memory apparatus includes memory cells each connected to one of a plurality of word lines and configured to store a threshold voltage corresponding to one of a plurality of data states. The memory apparatus also includes a control means configured to identify ones of the plurality of word lines as slow word lines. The control means is also configured to ramp at least one program pulse applied to the slow word lines to a program kick voltage higher in magnitude than a program voltage for a program kick period of time during at least one program loop of a program operation.
1 . A memory apparatus, comprising:
memory cells each connected to one of a plurality of word lines and configured to store a threshold voltage corresponding to one of a plurality of data states; and
a control means configured to:
identify ones of the plurality of word lines as slow word lines, and
ramp at least one program pulse applied to the slow word lines to a program kick voltage higher in magnitude than a program voltage for a program kick period of time during at least one program loop of a program operation.
2 . The memory apparatus as set forth in claim 1 , further including a design for test circuit configured to measure a word line potential ramp rate over a word line potential ramp time for each of the plurality of word lines, wherein the control means is further configured to:
detect the word line potential ramp rate over the word line potential ramp time for the ones of the plurality of word lines using the design for test circuit while the at least one program pulse is applied to the ones of the plurality of word lines; and
identify the ones of the plurality of word lines as the slow word lines based on the word line potential ramp rate over the word line potential ramp time detected for the ones of the plurality of word lines.
3 . The memory apparatus as set forth in claim 2 , wherein the control means is further configured to ramp other voltages applied to the slow word lines besides the at least one program pulse for a kick period of time during the at least one program loop to a kick voltage higher in magnitude for the slow word lines ramping up and lower in magnitude for the slow word lines ramping down for a kick period of time during the at least one program loop of the program operation.
4 . The memory apparatus as set forth in claim 3 , wherein the control means is further configured to vary a magnitude of at least one of the kick voltage of the other voltages or a magnitude of the program kick voltage of the at least one program pulse based on a percentage change between an earlier voltage of the slow word lines prior to ramping and the at least one of the kick voltage or the program kick voltage.
5 . The memory apparatus as set forth in claim 3 , wherein the control means is further configured to:
quantify a slowness of the slow word lines according to the word line potential ramp rate over the word line potential ramp time detected for the ones of the plurality of word lines; and
vary a magnitude of at least one of the kick voltage of the other voltages or a magnitude of the program kick voltage of the at least one program pulse based on the slowness of the slow word lines.
6 . The memory apparatus as set forth in claim 1 , wherein the at least one program loop of the program operation includes a plurality of program loops, the memory cells are disposed in memory holes grouped into a plurality of strings, and the control means is further configured to:
identify the ones of the plurality of word lines as the slow word lines in a first one of the plurality of program loops for one of the plurality of strings; and
utilize the identification of the ones of the plurality of word lines as the slow word lines for the one of the plurality of strings for other ones of the plurality of strings during subsequent ones of the plurality of program loops.
7 . The memory apparatus as set forth in claim 1 , wherein the control means is further configured to ramp the at least one program pulse applied to the slow word lines to the program kick voltage higher in magnitude than the program voltage for the program kick period of time in a stepwise fashion with a plurality of ramp steps lasting each of a plurality of ramp time periods during the at least one program loop of the program operation.
8 . A controller in communication with a memory apparatus including memory cells each connected to one of a plurality of word lines and configured to store a threshold voltage corresponding to one of a plurality of data states, the controller configured to:
identify ones of the plurality of word lines as slow word lines; and
instruct the memory apparatus to ramp at least one program pulse applied to the slow word lines to a program kick voltage higher in magnitude than a program voltage for a program kick period of time during at least one program loop of a program operation.
9 . The controller as set forth in claim 8 , wherein the memory apparatus further includes a design for test circuit configured to measure a word line potential ramp rate over a word line potential ramp time for each of the plurality of word lines, and the controller is further configured to:
instruct the memory apparatus to detect the word line potential ramp rate over the word line potential ramp time for the ones of the plurality of word lines using the design for test circuit while the at least one program pulse is applied to the ones of the plurality of word lines; and
identify the ones of the plurality of word lines as the slow word lines based on the word line potential ramp rate over the word line potential ramp time detected for the ones of the plurality of word lines.
10 . The controller as set forth in claim 9 , wherein the controller is further configured to instruct the memory apparatus to ramp other voltages applied to the slow word lines besides the at least one program pulse for a kick period of time during the at least one program loop to a kick voltage higher in magnitude for the slow word lines ramping up and lower in magnitude for the slow word lines ramping down for a kick period of time during the at least one program loop of the program operation.
11 . The controller as set forth in claim 10 , wherein the controller is further configured to instruct the memory apparatus to vary a magnitude of at least one of the kick voltage of the other voltages or a magnitude of the program kick voltage of the at least one program pulse based on a percentage change between an earlier voltage of the slow word lines prior to ramping and the at least one of the kick voltage or the program kick voltage.
12 . The controller as set forth in claim 10 , wherein the controller is further configured to:
quantify a slowness of the slow word lines according to the word line potential ramp rate over the word line potential ramp time detected for the ones of the plurality of word lines; and
instruct the memory apparatus to vary a magnitude of at least one of the kick voltage of the other voltages or a magnitude of the program kick voltage of the at least one program pulse based on the slowness of the slow word lines.
13 . The controller as set forth in claim 8 , wherein the controller is further configured to instruct the memory apparatus to ramp the at least one program pulse applied to the slow word lines to the program kick voltage higher in magnitude than the program voltage for the program kick period of time in a stepwise fashion with a plurality of ramp steps lasting each of a plurality of ramp time periods during the at least one program loop of the program operation.
14 . A method of operating a memory apparatus including memory cells each connected to one of a plurality of word lines and configured to store a threshold voltage corresponding to one of a plurality of data states; the method comprising the steps of:
identifying ones of the plurality of word lines as slow word lines; and
ramping at least one program pulse applied to the slow word lines to a program kick voltage higher in magnitude than a program voltage for a program kick period of time during at least one program loop of a program operation.
15 . The method as set forth in claim 14 , wherein the memory apparatus further includes a design for test circuit configured to measure a word line potential ramp rate over a word line potential ramp time for each of the plurality of word lines, and the method further includes the steps of:
detecting the word line potential ramp rate over the word line potential ramp time for the ones of the plurality of word lines using the design for test circuit while the at least one program pulse is applied to the ones of the plurality of word lines; and
identifying the ones of the plurality of word lines as the slow word lines based on the word line potential ramp rate over the word line potential ramp time detected for the ones of the plurality of word lines.
16 . The method as set forth in claim 15 , further including the step of ramping other voltages applied to the slow word lines besides the at least one program pulse for a kick period of time during the at least one program loop to a kick voltage higher in magnitude for the slow word lines ramping up and lower in magnitude for the slow word lines ramping down for a kick period of time during the at least one program loop of the program operation.
17 . The method as set forth in claim 16 , further including the step of varying a magnitude of at least one of the kick voltage of the other voltages or a magnitude of the program kick voltage of the at least one program pulse based on a percentage change between an earlier voltage of the slow word lines prior to ramping and the at least one of the kick voltage or the program kick voltage.
18 . The method as set forth in claim 16 , further including the steps of:
quantifying a slowness of the slow word lines according to the word line potential ramp rate over the word line potential ramp time detected for the ones of the plurality of word lines; and
varying a magnitude of at least one of the kick voltage of the other voltages or a magnitude of the program kick voltage of the at least one program pulse based on the slowness of the slow word lines.
19 . The method as set forth in claim 14 , wherein the at least one program loop of the program operation includes a plurality of program loops, the memory cells are disposed in memory holes grouped into a plurality of strings, and the method further includes the steps of:
identifying the ones of the plurality of word lines as the slow word lines in a first one of the plurality of program loops for one of the plurality of strings; and
utilizing the identification of the ones of the plurality of word lines as the slow word lines for the one of the plurality of strings for other ones of the plurality of strings during subsequent ones of the plurality of program loops.
20 . The method as set forth in claim 14 , further including the step of ramping the at least one program pulse applied to the slow word lines to the program kick voltage higher in magnitude than the program voltage for the program kick period of time in a stepwise fashion with a plurality of ramp steps lasting each of a plurality of ramp time periods during the at least one program loop of the program operation.