Scan circuit and method
In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.
1. An integrated circuit (IC) comprising:
a plurality of logic circuits (ICs); and
a scan circuit, wherein the integrated circuit (IC) is configured to:
enter scan mode of the IC,
receive a test pattern,
select a sub-scan chain to become part of a first scan chain,
apply the test pattern through the first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain,
while applying the test pattern through the first scan chain, control an unselected sub-scan chain with the first scan chain without transitioning a scan enable input of a scan flip-flop of the unselected sub-scan chain, wherein the selected sub-scan chain has a length of N, the unselected sub-scan chain has a length of N, and N is a positive integer greater than or equal to 1, and
evaluate an output of the first scan chain to detect faults of the IC.
2. The integrated circuit of claim 1 , wherein the first scan chain has a length of N.
3. The integrated circuit of claim 1 , further comprising an logic built-in-self-test (LBIST) controller configured to provide the test pattern.
4. The integrated circuit of claim 1 , further comprising an OR gate having an output coupled the further scan enable input of the further scan flip-flop, the output of the OR gate being indicative of whether the integrated circuit is in scan mode.
5. The integrated circuit of claim 1 , wherein the scan circuit further comprises a multiplexer (MUX) having a first input coupled to an output of a scan flip-flop of the first scan chain, a second input coupled to an output of the further scan flip-flop, and an output coupled to the first scan chain.
6. The integrated circuit of claim 5 , further comprising a second further scan flip-flop having an output coupled to a selection input of the MUX.
7. The integrated circuit of claim 6 , wherein the second further scan flip-flop is part of a second scan chain different form the first scan chain.
8. The integrated circuit of claim 6 , further comprising a third further scan flip-flop having a clock input coupled to a scan enable input of the second further scan flip-flop, and an output coupled to the selection input of the MUX.
9. The integrated circuit of claim 6 , further comprising a latch coupled between the second further scan flip-flop and the selection input of the MUX.
10. An integrated circuit (IC) comprising:
a plurality of logic circuits (ICs); and
a scan circuit, wherein the integrated circuit (IC) is configured to:
enter scan mode of an integrated circuit (IC),
receive test patterns,
decompress the test patterns,
dynamically select scan chains from a plurality of scan chains,
apply the decompressed test patterns to the selected scan chains by pulsing a clock signal and transitioning a scan enable signal coupled to the selected scan chains,
apply the decompressed test patterns to unselected scan chains without transitioning a scan enable signal coupled to the unselected scan chains,
compress outputs of the plurality of scan chains, and
evaluate the compressed outputs to detect faults of the IC.
11. The integrated circuit of claim 10 , further comprising an logic built-in-self-test (LBIST) controller configured to provide the test pattern.
12. The integrated circuit of claim 10 , further comprising an OR gate having an output coupled the further scan enable input of the further scan flip-flop, the output of the OR gate being indicative of whether the integrated circuit is in scan mode.
13. The integrated circuit of claim 10 , wherein the scan circuit further comprises a multiplexer (MUX) having a first input coupled to an output of a scan flip-flop of a first scan chain of the plurality of scan chains, a second input coupled to an output of the further scan flip-flop, and an output coupled to the first scan chain.
14. The integrated circuit of claim 13 , further comprising a second further scan flip-flop having an output coupled to a selection input of the MUX.
15. The integrated circuit of claim 14 , wherein the second further scan flip-flop is part of a second scan chain different form the first scan chain.
16. The integrated circuit of claim 14 , further comprising a third further scan flip-flop having a clock input coupled to a scan enable input of the second further scan flip-flop, and an output coupled to the selection input of the MUX.
17. The integrated circuit of claim 14 , further comprising a latch coupled between the second further scan flip-flop and the selection input of the MUX.
18. A method for detecting faults in an integrated circuit (IC), the method comprising:
coupling a Q output of a first scan flip-flop of a first scan chain to an SI input of second scan flip-flop, the Q output of the first scan flip-flop being a primary data output terminal of the first scan flip-flop, the SI input of the second scan flip-flop being a scan data input terminal of the second scan flip-flop that receives data during scan operations when a scan enable signal is asserted, the first scan chain having a first length upon coupling the Q output of the first scan flip-flop to the SI input of the second scan flip-flop and coupled to a first logic circuit;
coupling a Q output of the second scan flip-flop to a second logic circuit, the Q output of the second scan flip-flop being a primary data output terminal of the second scan flip-flop; and
coupling the Q output of the second scan flip-flop to an SI input of a third scan flip-flop of the first scan chain via a multiplexer, the SI input of the third scan flip-flop being a scan data input terminal of the third scan flip-flop that receives data during scan operations when a scan enable signal is asserted, wherein a length of the first scan chain is the first length upon selecting the second scan flip-flop by the multiplexer.
19. The method of claim 18 , wherein the second scan flip-flop is coupled to the first and the third scan flip-flops after a scan insertion, the scan insertion comprising performing an initial scan circuit implementation and timing closure on the integrated circuit.
20. The method of claim 18 , wherein the second scan enable input of the second scan flip-flop is kept asserted while applying a test pattern through the first scan chain.