IP Library › Granted Patent US 12,563,759
Granted Patent B2
US 12,563,759 · App. 18/453,482 · Granted Feb 24, 2026

Semiconductor module

Inventors: Kento Adachi (Ota, JP); Tatsunori Sakano (Shinagawa, JP)
Assignees: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
H10D12/481H10D62/10H10D64/513
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,563,759
App. No.
18/453,482
Granted
Feb 24, 2026
Kind
B2
Abstract

A voltage of a third gate electrode of a first semiconductor device transitions from a first off-voltage that is not more than a threshold voltage to a second off-voltage lower than the first off-voltage during a period from when a pulse signal for turning off a first gate electrode and a second gate electrode of the first semiconductor device is input to a drive device to when any one of a first gate electrode, a second gate electrode, and a third gate electrode of a second semiconductor device reaches an on-voltage.

Claims (35)

1 . A semiconductor module comprising:

a first semiconductor device and a second semiconductor device each having a first gate electrode, a second gate electrode, and a third gate electrode, the first gate electrode, the second gate electrode, and the third gate electrode being controlled independently of one another, and during a period from when the first gate electrode is turned on to when the first gate electrode is turned off, an on-period of the second gate electrode being shorter than an on-period of the first gate electrode, and an on-period of the third gate electrode being shorter than the on-period of the second gate electrode; and

a drive device configured to drive the first semiconductor device and the second semiconductor device,

a voltage of the third gate electrode of the first semiconductor device transitioning from a first off-voltage that is not more than a threshold voltage to a second off-voltage lower than the first off-voltage during a period from when a pulse signal for turning off the first gate electrode and the second gate electrode of the first semiconductor device is input to the drive device to when any one of the first gate electrode, the second gate electrode, and the third gate electrode of the second semiconductor device reaches an on-voltage, and

a voltage of the third gate electrode of the second semiconductor device transitioning from a third off-voltage that is not more than a threshold voltage to a fourth off-voltage lower than the third off-voltage during a period from when a pulse signal for turning off the first gate electrode and the second gate electrode of the second semiconductor device is input to the drive device to when any one of the first gate electrode, the second gate electrode, and the third gate electrode of the first semiconductor device reaches an on-voltage.

2 . The module according to claim 1 , wherein

after the voltage of the third gate electrode of the first semiconductor device transitions to the second off-voltage and the first gate electrode and the second gate electrode of the second semiconductor device are turned on, the voltage of the third gate electrode of the first semiconductor device returns to the first off-voltage during a period up to when the first gate electrode and the second gate electrode of the first semiconductor device are turned on, and

after the voltage of the third gate electrode of the second semiconductor device transitions to the fourth off-voltage and the first gate electrode and the second gate electrode of the first semiconductor device are turned on, the voltage of the third gate electrode of the second semiconductor device returns the third off-voltage during a period up to when the first gate electrode and the second gate electrode of the second semiconductor device are turned on.

3 . The module according to claim 1 , wherein

the voltage of the third gate electrode of the first semiconductor device transitions from the first off-voltage to the second off-voltage after a voltage of the first gate electrode and a voltage of the second gate electrode of the first semiconductor device are not more than a threshold voltage, and

the voltage of the third gate electrode of the second semiconductor device transitions from the third off-voltage to the fourth off-voltage after a voltage of the first gate electrode and a voltage of the second gate electrode of the second semiconductor device are not more than a threshold voltage.

4 . The module according to claim 1 , wherein

the voltage of the third gate electrode of the first semiconductor device transitions from the first off-voltage to the second off-voltage after the first gate electrode and the second gate electrode of the first semiconductor device are turned off, and

the voltage of the third gate electrode of the second semiconductor device transitions from the third off-voltage to the fourth off-voltage after the first gate electrode and the second gate electrode of the second semiconductor device are turned off.

5 . The module according to claim 1 , wherein

the voltage of the third gate electrode of the first semiconductor device transitions from the first off-voltage to the second off-voltage during a period up to when a voltage of any one of the first gate electrode, the second gate electrode, and the third gate electrode of the second semiconductor device reaches a threshold voltage, and

the voltage of the third gate electrode of the second semiconductor device transitions from the third off-voltage to the fourth off-voltage during a period up to when a voltage of any one of the first gate electrode, the second gate electrode, and the third gate electrode of the first semiconductor device reaches a threshold voltage.

6 . The module according to claim 1 , wherein

the voltage of the third gate electrode of the first semiconductor device transitions from the first off-voltage to the second off-voltage during a period up to when a voltage of any one of the first gate electrode, the second gate electrode, and the third gate electrode of the second semiconductor device is higher than an off-voltage, and

the voltage of the third gate electrode of the second semiconductor device transitions from the third off-voltage to the fourth off-voltage during a period up to when a voltage of any one of the first gate electrode, the second gate electrode, and the third gate electrode of the first semiconductor device is higher than an off-voltage.

7 . The module according to claim 1 , wherein

the first semiconductor device and the second semiconductor device are insulated gate bipolar transistors, and

an emitter electrode of the first semiconductor device is connected to a collector electrode of the second semiconductor device.

8 . The module according to claim 1 , wherein

the second off-voltage and the fourth off-voltage are negative voltages.

9 . The module according to claim 8 , wherein

a voltage of the first gate electrode and a voltage of the second gate electrode of the first semiconductor device when the first semiconductor device is turned off are negative voltages, and

a voltage of the first gate electrode and a voltage of the second gate electrode of the second semiconductor device when the second semiconductor device is turned off are negative voltages.

10 . The module according to claim 1 , further comprising:

a pulse generator having an output connected to an input of the drive device.

11 . A semiconductor module comprising:

a first semiconductor device and a second semiconductor device each having a first gate electrode, a second gate electrode, and a third gate electrode, the first gate electrode, the second gate electrode, and the third gate electrode being controlled independently of one another, and during a period from when the first gate electrode is turned on to when the first gate electrode is turned off, an on-period of the second gate electrode being shorter than an on-period of the first gate electrode, and an on-period of the third gate electrode being shorter than the on-period of the second gate electrode; and

a drive device configured to drive the first semiconductor device and the second semiconductor device,

a voltage of the third gate electrode of the first semiconductor device transitioning from a first off-voltage that is not more than a threshold voltage to a second off-voltage lower than the first off-voltage during a period from when the first gate electrode and the second gate electrode of the first semiconductor device are turned off to when any one of the first gate electrode, the second gate electrode, and the third gate electrode of the second semiconductor device reaches an on-voltage, and

a voltage of the third gate electrode of the second semiconductor device transitioning from a third off-voltage that is not more than a threshold voltage to a fourth off-voltage lower than the third off-voltage during a period from when the first gate electrode and the second gate electrode of the second semiconductor device are turned off to when any one of the first gate electrode, the second gate electrode, and the third gate electrode of the first semiconductor device reaches an on-voltage.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2023
From: ADACHI, KENTO; SAKANO, TATSUNORI
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 064664/0951 →
Priority Claims (1)
JP 2023-014047 · Feb 1, 2023 · national
Continuity (1)
Related Publication 20240258411A1 · Aug 1, 2024
References Cited (4)
US 11374563B2 · Sakano · 2022 [cited by examiner]
US 12362746B2 · Adachi · 2025 [cited by examiner]
US 20210281258A1 · Sakano · 2021 [cited by examiner]
JP 2021141304A · 2021 [cited by applicant]