IP Library › Granted Patent US 12,362,746
Granted Patent B2
US 12,362,746 · App. 18/452,810 · Granted Jul 15, 2025

Semiconductor drive device and semiconductor module

Inventors: Kento Adachi (Tokyo, JP); Tatsunori Sakano (Tokyo, JP)
Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
H03K17/567H03K2217/0036
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Quick Facts
Patent No.
US 12,362,746
App. No.
18/452,810
Granted
Jul 15, 2025
Kind
B2
Abstract

The semiconductor drive device includes a third turn-off gate resistor that is electrically connected to the third gate electrode of each of the first semiconductor device and the second semiconductor device, and that is inserted into a third turn-off interconnect configured to apply a potential for turning off the third gate electrode. And R CGsoff ≤ Vth ⁢ 3 min ⁡ ( C CGsgc ) ⁢ dv dt ( 1 ) where, in each of the first semiconductor device and the second semiconductor device, a threshold voltage of the third gate electrode being Vth3, a resistance value of the third turn-off gate resistor being R CGsoff , a minimum value of a capacitance between the third gate electrode and the collector electrode in a voltage dependence characteristic being min (C CGsgc ), and a time displacement of a voltage at a time of turning on being dv/dt.

Claims (234)

1. A semiconductor drive device for driving a first semiconductor device and a second semiconductor device each including a collector electrode, an emitter electrode, a first gate electrode, a second gate electrode, and a third gate electrode,

the first gate electrode, the second gate electrode, and the third gate electrode being independently controlled,

in a period from when the first gate electrode is turned on to when the first gate electrode is turned off, a turn-on period of the second gate electrode being less than a turn-on period of the first gate electrode, and a turn-on period of the third gate electrode being less than the turn-on period of the second gate electrode,

the semiconductor drive device comprising a third turn-off gate resistor that is electrically connected to the third gate electrode of each of the first semiconductor device and the second semiconductor device, and that is inserted into a third turn-off interconnect configured to apply a potential for turning off the third gate electrode, and

R

CGsoff

≤

Vth

⁢

3

min

⁡

(

C

CGsgc

)

⁢

dv

dt

(

1

)

where, in each of the first semiconductor device and the second semiconductor device, a threshold voltage of the third gate electrode being Vth3, a resistance value of the third turn-off gate resistor being R CGsoff , a minimum value of a capacitance between the third gate electrode and the collector electrode in a voltage dependence characteristic being min (C CGsgc ), and a time displacement of a voltage at a time of turning on being dv/dt.

2. The device according to claim 1 , wherein

R

CGsoff

≤

Vth

⁢

3

(

min

⁡

(

C

CGsgc

)

+

max

⁡

(

C

CGsgc

)

)

2

×

dv

dt

(

2

)

where a maximum value of the capacitance between the third gate electrode and the collector electrode in the voltage dependence characteristic is max (C CGsgc ).

3. The device according to claim 2 , wherein

R

CGsoff

≤

Vth

⁢

3

max

⁡

(

C

CGsgc

)

⁢

dv

dt

.

(

3

)

4. The device according to claim 1 , further comprising:

a first turn-off gate resistor that is electrically connected to the first gate electrode of each of the first semiconductor device and the second semiconductor device and is inserted into a first turn-off interconnect configured to apply a potential for turning off the first gate electrode, and

R CGsoff C CGsgc ≤R MGoff C MGgc   (4)

where, in each of the first semiconductor device and the second semiconductor device, the capacitance between the third gate electrode and the collector electrode being C CGsgc , a resistance value of the first turn-off gate resistor being R MGoff , and a capacitance between the first gate electrode and the collector electrode being C MGgc .

5. The device according to claim 3 , further comprising:

a first turn-off gate resistor that is electrically connected to the first gate electrode of each of the first semiconductor device and the second semiconductor device and that is inserted into a first turn-off interconnect configured to apply a potential for turning off the first gate electrode, and

Vth

⁢

1

max

⁡

(

C

MGgc

)

⁢

dv

dt

≤

R

MGoff

(

5

)

where, in each of the first semiconductor device and the second semiconductor device, a threshold voltage of the first gate electrode being Vth1, a resistance value of the first turn-off gate resistor being R MGoff , and a maximum value of a capacitance between the first gate electrode and the collector electrode in the voltage dependence characteristic being max (C MGgc ).

6. The device according to claim 3 , further comprising:

a first turn-off gate resistor that is electrically connected to the first gate electrode of each of the first semiconductor device and the second semiconductor device and that is inserted into a first turn-off interconnect configured to apply a potential for turning off the first gate electrode, and

Vth

⁢

1

max

⁡

(

C

MGgc

)

⁢

dv

dt

≤

R

MGoff

≤

Vth

⁢

1

+

❘

"\[LeftBracketingBar]"

V

-

GE

❘

"\[RightBracketingBar]"

min

⁡

(

C

MGgc

)

⁢

dv

dt

(

6

)

where, in each of the first semiconductor device and the second semiconductor device, a threshold voltage of the first gate electrode being Vth1, a resistance value of the first turn-off gate resistor being R MGoff , a maximum value of a capacitance between the first gate electrode and the collector electrode in the voltage dependence characteristic being max (C MGgc ), a minimum value of the capacitance between the first gate electrode and the collector electrode in the voltage dependence characteristic being min (C MGgc ), and a voltage between the first gate electrode and the emitter electrode being V −GE .

7. A semiconductor module comprising:

a first semiconductor device and a second semiconductor device each including a collector electrode, an emitter electrode, a first gate electrode, a second gate electrode, and a third gate electrode, the first gate electrode, the second gate electrode, and the third gate electrode being controlled independently, and in a period from when the first gate electrode is turned on to when the first gate electrode is turned off, a turn-on period of the second gate electrode being less than a turn-on period of the first gate electrode, and a turn-on period of the third gate electrode being less than the turn-on period of the second gate electrode; and

a semiconductor drive device configured to drive the first semiconductor device and the second semiconductor device,

the semiconductor drive device including a third turn-off gate resistor that is electrically connected to the third gate electrode of each of the first semiconductor device and the second semiconductor device and that is inserted into a third turn-off interconnect configured to apply a potential for turning off the third gate electrode, and

R

CGsoff

≤

Vth

⁢

3

min

⁡

(

C

CGsgc

)

⁢

dv

dt

(

1

)

where, in each of the first semiconductor device and the second semiconductor device, a threshold voltage of the third gate electrode being Vth3, a resistance value of the third turn-off gate resistor being R CGsoff , a minimum value of a capacitance between the third gate electrode and the collector electrode in a voltage dependence characteristic being min (C CGsgc ), and a time displacement of a voltage at a time of turning on being dv/dt.

8. A semiconductor module comprising:

the semiconductor drive device according to claim 3 ;

the first semiconductor device; and

the second semiconductor device.

9. The module according to claim 8 , wherein

the semiconductor drive device includes a first turn-off gate resistor that is electrically connected to the first gate electrode of each of the first semiconductor device and the second semiconductor device and that is inserted into a first turn-off interconnect configured to apply a potential for turning off the first gate electrode, and

R CGsoff C CGsgc ≤R MGoff C MGgc   (4)

where, in each of the first semiconductor device and the second semiconductor device, the capacitance between the third gate electrode and the collector electrode is C CGsgc , a resistance value of the first turn-off gate resistor is R MGoff , and a capacitance between the first gate electrode and the collector electrode is C MGgc .

10. The module according to claim 8 , wherein

the semiconductor drive device includes a first turn-off gate resistor that is electrically connected to the first gate electrode of each of the first semiconductor device and the second semiconductor device and that is inserted into a first turn-off interconnect configured to apply a potential for turning off the first gate electrode, and

Vth

⁢

1

max

⁡

(

C

MGgc

)

⁢

dv

dt

≤

R

MGoff

(

5

)

where, in each of the first semiconductor device and the second semiconductor device, a threshold voltage of the first gate electrode is Vth1, a resistance value of the first turn-off gate resistor is R MGoff , and a maximum value of a capacitance between the first gate electrode and the collector electrode in the voltage dependence characteristic is max (C MGgc ).

11. The module according to claim 8 , wherein

the semiconductor drive device includes a first turn-off gate resistor that is electrically connected to the first gate electrode of each of the first semiconductor device and the second semiconductor device and that is inserted into a first turn-off interconnect configured to apply a potential for turning off the first gate electrode, and

Vth

⁢

1

max

⁡

(

C

MGgc

)

⁢

dv

dt

≤

R

MGoff

≤

Vth

⁢

1

+

❘

"\[LeftBracketingBar]"

V

-

GE

❘

"\[RightBracketingBar]"

min

⁡

(

C

MGgc

)

⁢

dv

dt

(

6

)

where, in each of the first semiconductor device and the second semiconductor device, a threshold voltage of the first gate electrode is Vth1, a resistance value of the first turn-off gate resistor is R MGoff , a maximum value of a capacitance between the first gate electrode and the collector electrode in the voltage dependence characteristic is max (C MGgc ), a minimum value of the capacitance between the first gate electrode and the collector electrode in the voltage dependence characteristic is min (C MGgc ), and a voltage between the first gate electrode and the emitter electrode is V −GE .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2023
From: ADACHI, KENTO; SAKANO, TATSUNORI
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 064657/0441 →
Priority Claims (1)
JP 2022-196535 · Dec 8, 2022 · national
Continuity (1)
Related Publication 20240195408A1 · Jun 13, 2024
References Cited (4)
US 20210281258A1 · Sakano · 2021 [cited by examiner]
JP H0832064A · 1996 [cited by examiner]
JP 2021141304A · 2021 [cited by applicant]
Machida, “Approaching the Limit of Switching Loss Reduction in Si-IGBTs”, 2014, ISPSD, IEEE, 4 pages. [cited by applicant]
Cited By (1)
US 12,563,759