Arbiter for non-persistent signals
Systems and devices for signal arbitration are described. A first asynchronous circuit can receive and sanitize a first non-persistent signal representing a first request to generate a first persistent signal. A second asynchronous circuit can receive and sanitize a second non-persistent signal representing a second request to generate a second persistent signal. A mutual exclusive circuit can arbitrate between the first persistent signal and the second persistent signal and output a grant signal to issue a grant. A control circuit can control an operation mode of the first and second asynchronous circuits based on a control signal, a first grant signal indicating a grant status of the first request, a second grant signal indicating a grant status of the second request, the first persistent signal and the second persistent signal.
1 . A semiconductor device comprising:
a first asynchronous circuit configured to:
receive a first non-persistent signal representing a first request; and
sanitize the first non-persistent signal to generate a first persistent signal;
a second asynchronous circuit configured to:
receive a second non-persistent signal representing a second request; and
sanitize the second non-persistent signal to generate a second persistent signal;
a mutual exclusive (MUTEX) circuit configured to:
arbitrate between the first persistent signal and the second persistent signal; and
output a grant signal to issue a grant to one of the first request and the second request; and
a control circuit configured to control an operation mode of the first asynchronous circuit and the second asynchronous circuit based on a control signal, a first grant signal indicating a grant status of the first request, a second grant signal indicating a grant status of the second request, the first persistent signal and the second persistent signal, wherein the control circuit comprises:
a NAND gate configured to receive an inverse of the control signal, the first persistent signal and the second persistent signal as inputs;
a C-element configured to receive the control signal and an output of the NAND gate as inputs;
a first two-level logic gate configured to:
receive the second persistent signal, the first grant signal and an output of the C-element as inputs; and
output a first operation mode control signal to control the first asynchronous circuit; and
a second two-level logic gate configured to:
receive the first persistent signal, the second grant signal and the output of the C-element as inputs; and
output a second operation mode control signal to control the second asynchronous circuit.
2 . The semiconductor device of claim 1 , wherein:
to sanitize the first non-persistent signal, the first asynchronous circuit is configured to:
in response to the first non-persistent signal being above a predefined threshold voltage for a predetermined amount of time, rise the first persistent signal to logic high; and
in response to the second non-persistent signal being above the predefined threshold voltage for the predetermined amount of time, rise the second persistent signal to logic high.
3 . The semiconductor device of claim 1 , wherein a gate delay provided by the control circuit is at most three gate delays.
4 . The semiconductor device of claim 1 , wherein:
in response to a rising transition of the first operation mode control signal, the first asynchronous circuit operates in a waiting mode;
in response to a falling transition of the first operation mode control signal, the first asynchronous circuit operates in a dormant mode;
in response to a rising transition of the second operation mode control signal, the second asynchronous circuit operates in the waiting mode; and
in response to a falling transition of the second operation mode control signal, the second asynchronous circuit operates in the dormant mode.
5 . The semiconductor device of claim 1 , further comprising:
a first NOR gate configured to:
receive the first non-persistent signal and the second grant signal as inputs; and
in response to the first non-persistent signal failing to be above a predefined threshold voltage for a predetermined amount of time, reset the first asynchronous circuit; and
a second NOR gate configured to:
receive the second non-persistent signal and the first grant signal as inputs; and
in response to the second non-persistent signal failing to be above the predefined threshold voltage for the predetermined amount of time, reset the second asynchronous circuit.
6 . A system comprising:
a first client;
a second client;
a resource; and
an arbiter comprising:
a first asynchronous circuit configured to:
receive a first non-persistent signal representing a first request from the first client; and
sanitize the first non-persistent signal to generate a first persistent signal;
a second asynchronous circuit configured to:
receive a second non-persistent signal representing a second request from the second client; and
sanitize the second non-persistent signal to generate a second persistent signal;
a mutual exclusive (MUTEX) circuit configured to:
arbitrate between the first persistent signal and the second persistent signal; and
output a grant signal to grant one of the first client and the second client to access the resource; and
a control circuit configured to control an operation mode of the first asynchronous circuit and the second asynchronous circuit based on a control signal, a first grant signal indicating a grant status of the first request, a second grant signal indicating a grant status of the second request, the first persistent signal and the second persistent signal, wherein the control circuit comprises:
a NAND gate configured to receive an inverse of the control signal, the first persistent signal and the second persistent signal as inputs;
a C-element configured to receive the control signal and an output of the NAND gate as inputs;
a first two-level logic gate configured to:
receive the second persistent signal, the first grant signal and an output of the C-element as inputs; and
output a first operation mode control signal to control the first asynchronous circuit; and
a second two-level logic gate configured to:
receive the first persistent signal, the second grant signal and the output of the C-element as inputs; and
output a second operation mode control signal to control the second asynchronous circuit.
7 . The system of claim 6 , wherein:
to sanitize the first non-persistent signal, the first asynchronous circuit is configured to:
in response to the first non-persistent signal being above a predefined threshold voltage for a predetermined amount of time, rise the first persistent signal to logic high; and
in response to the second non-persistent signal being above the predefined threshold voltage for the predetermined amount of time, rise the second persistent signal to logic high.
8 . The system of claim 6 , wherein a gate delay provided by the control circuit is at most three gate delays.
9 . The system of claim 6 , wherein:
in response to a rising transition of the first operation mode control signal, the first asynchronous circuit operates in a waiting mode;
in response to a falling transition of the first operation mode control signal, the first asynchronous circuit operates in a dormant mode;
in response to a rising transition of the second operation mode control signal, the second asynchronous circuit operates in the waiting mode; and
in response to a falling transition of the second operation mode control signal, the second asynchronous circuit operates in the dormant mode.
10 . The system of claim 6 , wherein the arbiter further comprises:
a first NOR gate configured to:
receive the first non-persistent signal and the second grant signal as inputs; and
in response to the first non-persistent signal failing to be above a predefined threshold voltage for a predetermined amount of time, reset the first asynchronous circuit; and
a second NOR gate configured to:
receive the second non-persistent signal and the first grant signal as inputs; and
in response to the second non-persistent signal failing to be above the predefined threshold voltage for the predetermined amount of time, reset the second asynchronous circuit.
11 . The system of claim 6 , wherein the first client, the second client, the resource and the arbiter are parts of an asynchronous system.
12 . A semiconductor device comprising:
N first asynchronous circuit configured to:
receive N non-persistent signals representing N requests; and
sanitize the N non-persistent signals to generate N persistent signals;
a mutual exclusive (MUTEX) circuit configured to:
arbitrate among the N persistent signals; and
output a grant signal to issue a grant to one of the N requests; and
a control circuit configured to control an operation mode of the N asynchronous circuits based on a control signal, N grant signals indicating grant status of the N requests and the N persistent signals, the control circuit comprises:
a NAND gate configured to receive an inverse of the control signal and the N persistent signals as inputs;
a C-element configured to receive the control signal and an output of the NAND gate as inputs; and
N multi-level logic gates configured to output N operation mode control signals to control the N asynchronous circuits.
13 . The semiconductor device of claim 12 , wherein to sanitize a non-persistent signal among the N non-persistent signals, a corresponding asynchronous circuit among the N asynchronous circuits is configured to, in response to the non-persistent signal being above a predefined threshold voltage for a predetermined amount of time, rise the persistent signal to logic high.
14 . The semiconductor device of claim 12 , wherein a gate delay provided by the control circuit is at most three gate delays.
15 . The semiconductor device of claim 12 , wherein:
in response to rising transitions of the N operation mode control signals, the N asynchronous circuits operate in a waiting mode; and
in response to falling transitions of the N operation mode control signals, the N asynchronous circuits operate in a dormant mode.
16 . The semiconductor device of claim 12 , further comprising N NOR gates, wherein each one of the N NOR gates is configured to, in response to a corresponding non-persistent signal failing to be above a predefined threshold voltage for a predetermined amount of time, reset a corresponding asynchronous circuit.
17 . The semiconductor device of claim 12 , wherein the N multi-level logic gates are three-level logic gates, and the control circuit is configured to reset the N asynchronous circuits concurrently.
18 . The semiconductor device of claim 12 , wherein the N multi-level logic gates are two-level logic gates, and the control circuit is configured to reset the N asynchronous circuits sequentially.