Sampling signals
An asynchronous circuit portion for sampling an input signal is provided. The asynchronous circuit portion comprises a sampling circuit portion arranged to receive the input signal and to generate first and second sample signals; a first storage element arranged to generate a first storage signal on a first storage output on reception of the first sample signal; and a second storage element arranged to generate a second storage signal on a second storage output on reception of the second sample signal. A control circuit portion is arranged to detect if either of said first and second storage signals has been generated, to fix the first and second storage outputs and to generate a sample ready signal. The circuit portion generates an output signal corresponding to the input signal using the first storage output when the sample ready signal is generated.
1 . An asynchronous circuit portion for sampling an input signal comprising:
a sampling circuit portion arranged to receive the input signal and generate a first sample signal if the input signal has a first state, and to generate a second sample signal if the input signal has a second state;
a first storage element arranged to receive the first sample signal and comprising a first storage output, wherein the first storage element is arranged to generate a first storage signal on the first storage output on reception of the first sample signal;
a second storage element arranged to receive the second sample signal and comprising a second storage element output, wherein the second storage element is arranged to generate a second storage signal on the second storage output on reception of the second sample signal; and
a control circuit portion arranged to detect if either of said first and second storage signals has been generated and, if either of the first or second storage signals has been generated, to fix the first and second storage outputs and to generate a sample ready signal; and
wherein the asynchronous circuit portion generates an output signal corresponding to the input signal using the first storage output and the sample ready signal indicates that the output signal is ready for use.
2 . The asynchronous circuit portion as claimed in claim 1 , arranged to sample the input signal on reception of a start signal.
3 . The asynchronous circuit portion as claimed in claim 2 , wherein the control circuit portion is arranged to enable the sampling circuit portion in response to receiving the start signal.
4 . The asynchronous circuit portion as claimed in claim 2 , wherein the control circuit portion is arranged to reset the first and second storage outputs in response to receiving the start signal.
5 . The asynchronous circuit portion as claimed in claim 2 , wherein the control circuit portion is arranged to de-assert the sample ready signal on detection of a de-assertion of the start signal.
6 . The asynchronous circuit portion as claimed in claim 1 , wherein the sampling circuit portion is arranged to generate the first sample signal if the input signal has a first state for a minimum duration.
7 . The asynchronous circuit portion as claimed in claim 1 , wherein the sampling circuit portion comprises a first sampling element arranged to receive the input signal and generate the first sample signal.
8 . The asynchronous circuit portion as claimed in claim 7 , wherein the first sampling element comprises a mutual exclusion element arranged to receive the input signal or an inverted version thereof as a first request input, an enable signal as a second request input, and to output the first sample signal as an output.
9 . The asynchronous circuit portion as claimed in claim 1 , wherein the control circuit portion is arranged to detect if either of the first and second storage signals has been generated by monitoring a combination of the first and second storage outputs.
10 . The asynchronous circuit portion as claimed in claim 9 , wherein the control circuit portion comprises a stored signal input connected to the first and second storage outputs via an OR gate, such that the stored signal input receives a signal when either of the first or second storage signals is generated.
11 . The asynchronous circuit portion as claimed in claim 1 , configured to provide the first storage output or a version thereof as the output signal.
12 . The asynchronous circuit portion as claimed in claim 1 , wherein the output signal comprises a persistent sample of the input signal.
13 . The asynchronous circuit portion as claimed in claim 12 , comprising an output storage element arranged to receive the first latch output, and output the first storage output as the output signal, wherein the sample ready signal indicates that the output signal is ready for use.
14 . The asynchronous circuit portion as claimed in claim 13 , wherein the control circuit portion is arranged to fix the output of the output storage element on reception of a start signal.
15 . The asynchronous circuit portion as claimed in claim 1 , wherein the first storage element comprises a latch or a flip-flop.
16 . The asynchronous circuit portion as claimed in claim 1 , wherein the sampling circuit portion is arranged to generate the second sample signal if the input signal has a second state for a minimum duration.
17 . The asynchronous circuit portion as claimed in claim 1 , wherein the sampling circuit portion comprises a second sampling element arranged to receive the input signal and generate the second sample signal.
18 . The asynchronous circuit portion as claimed in claim 17 , wherein the second sampling element comprises a mutual exclusion element arranged to receive the input signal or an inverted version thereof as a first request input, an enable signal as a second request input, and to output the second sample signal as an output.
19 . The asynchronous circuit portion as claimed in claim 1 , wherein the second storage element comprises a latch or a flip-flop.