Semiconductor package including connection of dummy pad and test pad
A semiconductor package includes a first semiconductor chip including first front connection pads on a first front surface, first rear connection pads and dummy pads on a first rear surface, and through-electrodes. The package includes a second semiconductor chip including second front connection pads and test pads on a second front surface, and a protective layer including openings exposing at least a portion of the second front connection pads and the test pads. The package includes bump structures electrically connecting the first rear connection pads and the second front connection pads, and an adhesive film surrounding at least a portion of each of the first rear connection pads, the dummy pads, and the bump structures. The dummy pads overlap the test pads in a direction perpendicular to the first rear surface, and a height of the dummy pads is greater than a height of the first rear connection pads.
1 . A semiconductor package comprising:
a first semiconductor chip including a first front surface and a first rear surface opposite to each other, the first semiconductor chip including first front connection pads on the first front surface, first rear connection pads and dummy pads adjacent to each other on the first rear surface, and through-electrodes electrically connecting at least some of the first front connection pads with at least some of the first rear connection pads;
a second semiconductor chip including a second front surface facing the first rear surface, the second semiconductor chip including second front connection pads and test pads adjacent to each other on the second front surface, and a protective layer including openings exposing at least a portion of each of the second front connection pads and the test pads;
bump structures between the first semiconductor chip and the second semiconductor chip, the bump structures electrically connecting the first rear connection pads and the second front connection pads; and
an adhesive film surrounding at least a portion of each of the first rear connection pads, at least a portion of each of the dummy pads, and at least a portion of each of the bump structures, the adhesive film between the first semiconductor chip and the second semiconductor chip, wherein,
the dummy pads overlap the test pads in a direction perpendicular to the first rear surface, and
a height of the dummy pads is greater than a height of the first rear connection pads.
2 . The semiconductor package of claim 1 , wherein the dummy pads and the first rear connection pads each include,
a seed layer on the first rear surface, and
a plating layer on the seed layer.
3 . The semiconductor package of claim 1 , wherein each of the dummy pads has a width equal to or narrower than a width of each of the openings exposing the test pads.
4 . The semiconductor package of claim 3 , wherein the dummy pads are in contact with the test pads in the openings.
5 . The semiconductor package of claim 1 , wherein the dummy pads and the test pads are spaced apart from each other.
6 . The semiconductor package of claim 5 , wherein the adhesive film is between the dummy pads and the test pads.
7 . The semiconductor package of claim 1 , wherein each of the test pads includes a protrusion.
8 . The semiconductor package of claim 7 , wherein
each of the dummy pads is in contact with the protrusion of a corresponding one of the test pads, and
the adhesive film is between each of the test pads and each of the dummy pads.
9 . The semiconductor package of claim 1 , wherein each of the bump structures comprises,
a pillar portion below a corresponding one of the second front connection pads, and
a solder portion below the pillar portion, the solder portion contacting a corresponding one of the first rear connection pads.
10 . The semiconductor package of claim 1 , wherein a height of each of the dummy pads is equal to or greater than a height of each of the bump structures.
11 . The semiconductor package of claim 1 , wherein a height of each of the dummy pads is in a range from 20 μm to 50 μm.
12 . The semiconductor package of claim 1 , wherein the test pads are electrically connected to adjacent second front connection pads.
13 . The semiconductor package of claim 1 , further comprising a plurality of connection bumps below the first front connection pads of the first semiconductor chip.
14 . A semiconductor package comprising:
a first semiconductor chip including first rear connection pads, dummy pads adjacent to at least some of the first rear connection pads, and through-electrodes electrically connected to the first rear connection pads;
a second semiconductor chip on the first semiconductor chip, the second semiconductor chip including second front connection pads facing the first rear connection pads, and test pads facing the dummy pads;
bump structures electrically connecting the first rear connection pads and the second front connection pads; and
an adhesive film filling a space between the first semiconductor chip and the second semiconductor chip,
wherein an interval between each of the dummy pads and each of the test pads facing each other, is shorter than an interval between each of the first rear connection pads and each of the second front connection pads facing each other.
15 . The semiconductor package of claim 14 , wherein the adhesive film surrounds a side surface of each of the bump structures and a side surface of each of the dummy pads.
16 . The semiconductor package of claim 14 , wherein
the second semiconductor chip further comprises a protective layer covering a front surface, and the second front connection pads and the test pads are on the front surface, and
the protective layer includes openings exposing at least a portion of each of the second front connection pads and at least a portion of each of the test pads.
17 . The semiconductor package of claim 16 , wherein the test pads exposed through the openings are in contact with at least one of the dummy pads or the adhesive film.
18 . A semiconductor package comprising:
a first semiconductor chip including first rear connection pads, dummy pads adjacent to at least some of the first rear connection pads, and through-electrodes electrically connected to the first rear connection pads;
a second semiconductor chip on the first semiconductor chip, the second semiconductor chip including second front connection pads facing the first rear connection pads, and test pads facing the dummy pads;
bump structures electrically connecting the first rear connection pads and the second front connection pads facing each other; and
an adhesive film surrounding at least a portion of each of the dummy pads and at least a portion of each of the bump structures, the adhesive film between the first semiconductor chip and the second semiconductor chip,
wherein upper surfaces of the dummy pads are higher than upper surfaces of the first rear connection pads.
19 . The semiconductor package of claim 18 , wherein
each of the bump structures comprises a pillar portion below a corresponding one of the second front connection pads, and a solder portion below the pillar portion, the solder portion contacting a corresponding one of the first rear connection pads, and
the upper surfaces of the dummy pads are higher than a boundary surface between the pillar portion and the solder portion.
20 . The semiconductor package of claim 18 , wherein the upper surfaces of the dummy pads are in contact with at least one of the adhesive film or the test pads.