PAM4 threshold phase engine

1. A method to reduce bit error rate in a PAM4 clock data recovery circuit, comprising:

sweeping down from an upper voltage threshold to determine a first reference voltage value;

detecting a first filtered analog output associated with the first reference voltage value, and storing the first reference voltage value;

sweeping up from a lower voltage threshold to determine a second reference voltage value;

detecting a second filtered analog output associated with the second reference voltage value, and storing the second reference voltage value; and

averaging the stored first reference voltage value and the stored second reference voltage value to determine a calculated threshold value.

2. The method of claim 1 , further comprising determining the upper voltage threshold associated with a first target value of a slicing level.

3. The method of claim 1 , further comprising determining the lower voltage threshold associated with a first target value of a slicing level.

4. The method of claim 1 , wherein the step of averaging the stored first reference voltage value and the stored second reference voltage value further comprises equally weighting the stored first reference voltage value relative to the stored second reference voltage value.

5. The method of claim 1 , wherein the step of detecting the first filtered analog output associated with the first reference voltage value further comprises retrieving a middle path phase from a clock data recovery module of a middle pathway associated with a reference voltage having a value of zero (0).

6. The method of claim 5 , wherein the middle path phase is generated as a function of timing information.

7. The method of claim 1 , wherein the step of detecting the second filtered analog output associated with the second reference voltage value further comprises retrieving a middle path phase from a clock data recovery module of a middle pathway associated with a reference voltage having a value of zero (0).

8. The method of claim 7 , wherein the middle path phase is generated as a function of timing information.

9. The method of claim 1 , wherein the step of sweeping down from the upper voltage threshold to determine the first reference voltage value further comprises applying an offset calibration to a first target value as a function of the upper voltage threshold.

10. The method of claim 1 , wherein the step of sweeping up from the lower voltage threshold to determine the second reference voltage value further comprises applying an offset calibration to a first target value as a function of the lower voltage threshold.

11. The method of claim 1 , further comprising determining a first phase value for the first filtered analog output that matches a phase of a target analog output, and a second phase value for the second filtered analog output that matches the phase of the target analog output.

12. The method of claim 11 , further comprising calculating an optimum phase by averaging the first phase value and the second phase value.

13. The method of claim 12 , wherein determining the first phase value comprises:

retrieving a middle path phase set by a clock data recovery module of a middle pathway associated with a reference voltage having a value of zero (0);

determining whether a phase of the first filtered analog output matches a phase of the first reference voltage value;

responsive to determining that the phase of the first filtered analog output does not match the phase of the first reference voltage value, adjusting the middle path phase.