CDR circuit and receiver of multilevel modulation method

1. A clock data recovery (CDR) circuit comprising:

a data determination circuit that receives a data signal for which each of a plurality of potential levels is associated with a value of 2 bits or more, the potential levels being separated by 3 or more first thresholds, and outputs a result of determination that determines a value of the data signal, based on a result of a first comparison that compares the 3 or more first thresholds with the data signal at timing synchronized with a clock signal;

a comparison circuit that outputs a result of a second comparison that compares the data signal with a second threshold at the timing;

a phase detection circuit that generates a phase difference signal indicating whether to advance or delay a phase of the clock signal, based on the result of the determination and the result of the second comparison, when a value of 3 consecutive symbols represents one data pattern that transits like a slope and when a combination of the value of the 3 symbols and the result of the second comparison at an intermediate symbol of the 3 symbols matches some prespecified combination of a plurality of combinations that the data pattern and the result of the second comparison at the intermediate symbol may take;

a filter that generates a phase adjusted value indicating an adjustment amount of the phase, based on the phase difference signal; and

a phase adjustment circuit that adjusts the phase based on the phase adjusted value.

2. The CDR circuit according to claim 1 , wherein

the some combination is a combination that is less likely to generate an erroneous phase difference signal than any combination other than the some combination, of the plurality of combinations.

3. The CDR circuit according to claim 1 , wherein

the phase detection circuit calculates a product of a result of addition that adds the generated phase difference signal to each of a plurality of pairs of the 3 symbols included in n (n≥4) consecutive symbols of the data signal, and a value obtained by dividing the number of the plurality of combinations by the number of the some combination, and

the filter generates the phase adjusted value based on the product.

4. The CDR circuit according to claim 1 , wherein

there is a plurality of patterns of the some combination, according to a difference in the number of combinations to be included, and a pattern with a smaller number of combinations to be included has a fewer combinations that become a factor to generate the erroneous phase difference signal, and

the phase detection circuit selects a pattern of the plurality of patterns.

5. The CDR circuit according to claim 4 , further comprising:

an adjusted value monitoring circuit that determines whether or not the phase adjusted value is fixed; and

a switching control circuit that instructs the phase detection circuit to select a pattern with a larger number of combinations to be included than a currently selected pattern, of the plurality of patterns, if the adjusted value monitoring circuit determines that the phase adjusted value is fixed.

6. The CDR circuit according to claim 5 , wherein

the adjusted value monitoring circuit determines whether or not the phase adjusted value falls within a predetermined threshold range,

the switching control circuit instructs the phase detection circuit to select a pattern with the smallest number of combinations to be included, of the plurality of patterns, if the adjusted value monitoring circuit determines that the phase adjusted value does not fall within the threshold range, and

the adjusted value monitoring circuit changes the threshold range so as to include the phase adjusted value, if the adjusted value monitoring circuit determines that the phase adjusted value does not fall within the threshold range.

7. The CDR circuit according to claim 1 , further comprising:

an offset application circuit that adds a positive or negative offset value to the phase adjusted value.

8. A receiver of a multilevel modulation method comprising:

an equalizing circuit that receives a first data signal for which each of a plurality of potential levels is associated with a value of 2 bits or more, the potential levels being separated by 3 or more first thresholds, performs equalization processing on the first data signal, and outputs a second data signal;

a data determination circuit that receives the second data signal and outputs a result of determination that determines a value of the second data signal, based on a result of a first comparison that compares the 3 or more first thresholds with the second data signal at timing synchronized with a clock signal;

a comparison circuit that outputs a result of a second comparison that compares the second data signal with a second threshold at the timing;

a phase detection circuit that generates a phase difference signal indicating whether to advance or delay a phase of the clock signal, based on the result of the determination and the result of the second comparison, when a value of 3 consecutive symbols represents one data pattern that transits like a slope and when a combination of the value of the 3 symbols and the result of the second comparison at an intermediate symbol of the 3 symbols matches some prespecified combination of a plurality of combinations that the data pattern and the result of the second comparison at the intermediate symbol may take;

a filter that generates a phase adjusted value indicating an adjustment amount of the phase, based on the phase difference signal; and

a phase adjustment circuit that adjusts the phase based on the phase adjusted value.