Semiconductor systems with data clock applied
A semiconductor system includes a controller, configured to: adjust a duty ratio of a data clock according to a system rate in a half rate section, generate a transmission data clock and, transmit the transmission data clock through a channel. The system also includes a semiconductor device configured to receive the transmission data clock through the channel as a reception data clock, and generate an internal data clock for a data input and output operation, based on the reception data clock.
1 . A semiconductor system comprising:
a controller configured to: adjust a duty ratio of a data clock according to a system rate; generate a transmission data clock; and transmit the transmission data clock through a channel; and
a semiconductor device configured to: receive the transmission data clock through the channel as a reception data clock; and generate an internal data clock for a data input and output operation, based on the reception data clock,
wherein the controller comprises a half rate section, which adjusts the duty ratio of the data clock according to the system rate, and
wherein the data clock is set to have a frequency corresponding to a rate lower than of a data input and output rate in the half rate section, and is set to have a frequency corresponding to the data input and output rate in a full rate section.
2 . The semiconductor system of claim 1 ,
wherein the data clock is set to have a frequency corresponding to ½ of a data input and output rate in the half rate section.
3 . The semiconductor system of claim 2 ,
wherein the data input and output rate is set to a rate at which the data input and output operation is performed, and is set to ‘N’ times the system rate, the ‘N’ being set to a multiple of 2.
4 . The semiconductor system of claim 2 ,
wherein the full rate section is entered after the half rate section is ended.
5 . The semiconductor system of claim 1 ,
wherein the controller includes a duty adjustment circuit configured to generate the transmission data clock, based on a section setting signal, system rate information, and the data clock.
6 . The semiconductor system of claim 5 ,
wherein the section setting signal is activated when the half rate section is set.
7 . The semiconductor system of claim 5 ,
wherein the system rate information includes information about the system rate.
8 . The semiconductor system of claim 5 , wherein the duty adjustment circuit is configured to:
generate the transmission data clock by adjusting the duty ratio of the data clock by a first duty ratio change when the system rate is set to a first system rate in the half rate section, and
generate the transmission data clock by adjusting the duty ratio of the data clock by a second duty ratio change when the system rate is set to a second system rate in the half rate section.
9 . The semiconductor system of claim 1 , wherein the semiconductor device includes:
a data clock buffer configured to buffer the reception data clock to generate the internal data clock; and
an input and output control circuit configured to perform a data input and output operation, based on the internal data clock.
10 . A semiconductor system comprising:
a controller configured to: adjust a duty ratio of a data clock according to a duty adjustment signal in a half rate section; generate a transmission data clock; and transmit the transmission data clock through a channel; and
a semiconductor device configured to: receive the transmission data clock through the channel as a reception data clock; generate an internal data clock for a data input and output operation, based on the reception data clock; and generate the duty adjustment signal, based on the reception data clock,
wherein the data clock is set to have a frequency corresponding to a rate lower than of a data input and output rate in the half rate section, and is set to have a frequency corresponding to the data input and output rate in a full rate section.
11 . The semiconductor system of claim 10 ,
wherein the data clock is set to have a frequency corresponding to ½ of a data input and output rate in the half rate section, and
wherein the full rate section is entered after the half rate section is ended.
12 . The semiconductor system of claim 11 ,
wherein the data input and output rate is set to a rate at which the data input and output operation is performed, and is set to ‘N’ times a system rate, the ‘N’ being set to a multiple of 2.
13 . The semiconductor system of claim 10 ,
wherein the duty adjustment signal includes an up adjustment signal and a down adjustment signal, and
wherein the controller includes a duty adjustment circuit configured to generate the transmission data clock, based on a section setting signal, the up adjustment signal, the down adjustment signal, and the data clock.
14 . The semiconductor system of claim 13 ,
wherein the duty adjustment circuit receives the up adjustment signal and the down adjustment signal through the channel.
15 . The semiconductor system of claim 13 , wherein the duty adjustment circuit is configured to:
generate the transmission data clock by increasing a duty ratio of the data clock when the up adjustment signal is activated in the half rate section, and
generate the transmission data clock by decreasing the duty ratio of the data clock when the down adjustment signal is activated in the half rate section.
16 . The semiconductor system of claim 10 ,
wherein the duty adjustment signal includes an up adjustment signal and a down adjustment signal, and
wherein the semiconductor device includes an adjustment control signal generation circuit configured to generate the up adjustment signal and the down adjustment signal by detecting a degree of attenuation of the reception data clock in a full rate section.
17 . The semiconductor system of claim 16 , wherein the adjustment control signal generation circuit includes:
a pulse extraction circuit configured to extract a pulse having a minimum pulse width and a minimum differential swing level among pulses included in the reception data clock as a minimum pulse; and
an up/down detection circuit configured to generate the up adjustment signal and the down adjustment signal by detecting the pulse width and differential swing level of the minimum pulse, based on a detection clock and a reference code.
18 . The semiconductor system of claim 17 , wherein the up/down detection circuit includes:
a detection code generation circuit configured to generate a sense code by counting a sense clock, based on the minimum pulse; and
a code comparison circuit configured to generate the up adjustment signal and the down adjustment signal by comparing the sense code with the reference code.
19 . The semiconductor system of claim 18 ,
wherein the detection code generation circuit generates the detection code that is set to have a code value corresponding to a pulse width of the minimum pulse.
20 . The semiconductor system of claim 18 , wherein the code comparison circuit is configured to:
activate the up adjustment signal when the sense code is smaller than the reference code, and
activate the down adjustment signal when the sense code is greater than the reference code.
21 . A semiconductor system comprising:
a controller configured to generate a data clock for controlling a data input and output operation to output the data clock through a channel,
wherein the controller is additionally configured to:
generate the data clock having a first frequency and a first duty ratio for a first section, and
generate the data clock having a second frequency and a second duty ratio for a second section after the first section,
wherein the first frequency and the second frequency are set to be different, and the first duty ratio and the second duty ratio are set to be different.
22 . The semiconductor system of claim 21 ,
wherein the second frequency corresponds to a data input and output rate.
23 . The semiconductor system of claim 22 ,
wherein the first frequency corresponds to ½ of the second frequency.
24 . The semiconductor system of claim 21 ,
wherein the first duty ratio is set to (50+α) %, and the α is set to a positive or negative number.
25 . The semiconductor system of claim 24 ,
wherein the second duty ratio is set to 50%.
26 . The semiconductor system of claim 21 ,
wherein the controller sets the first section and the second section, based on a section setting signal.
27 . The semiconductor system of claim 21 ,
wherein the controller adjusts the first duty ratio according to a system rate.