Clock generation circuit capable of setting or controlling duty ratio of clock signal and system including clock generation circuit
A clock generation circuit receives a reference clock signal for outputting clock signals to peripheral circuits. A duty ratio of at least one of output buffer signals output from buffer circuits included in the clock generation circuit is varied so that a duty ratio of at least one of the clock signals can be varied.
1. A semiconductor device having plural function modules and a clock generation circuit, which supplies a clock generated therein to each of the function modules and comprises:
a frequency-multiplying circuit receiving an input of a reference clock signal and outputting a same-frequency or frequency-multiplied clock signal of said reference clock signal; and
a buffering portion buffering said output clock signal, wherein
said buffering portion includes at least one buffer circuit buffering said output clock signal such that a logic low period and a logic high period of said output clock signal are different from each other, and the difference between the logic low period and the logic high period of said output clock signal is maintained under a predetermined level of a control signal, wherein
at least one of a power supply potential or a reference potential in said buffer circuit is different from another power supply voltage or reference voltage, respectively, in said buffering portion.
2. A semiconductor device including plural function modules and a clock generation circuit, which supplies a clock generated therein to each of the function modules and comprises:
a frequency-multiplying circuit receiving an input of a reference clock signal and outputting a same-frequency or frequency-multiplied clock signal of said reference clock signal; and
a buffering portion buffering said output clock signal, wherein
said buffering portion includes at least one buffer circuit buffering said output clock signal such that a logic low period and a logic high period of said output clock signal are different from each other, and the difference between the logic low period and the logic high period of said output clock signal is maintained under a predetermined level of a control signal, wherein
a substrate potential of a transistor included in said buffer circuit is different from a substrate potential of another transistor included in said buffering portion.
3. A semiconductor device including plural function modules and a clock generation circuit, which supplies a clock generated therein to each of the function modules and comprises:
a frequency-multiplying circuit receiving an input of a reference clock signal and outputting a same-frequency or frequency-multiplied clock signal of said reference clock signal, said output clock signal having a logic high period and a logic low period different from each other; and
a buffering portion buffering said output clock signal, wherein
said frequency-multiplied circuit includes
a ring oscillator,
a comparator comparing a phase of said output clock signal output from said ring oscillator with a phase of said reference clock signal,
a counter determining a digital count value based on a phase comparison result output from said comparator, and
a control circuit incrementing/decrementing said digital count value in response to a rising/falling of said reference clock signal,
said ring oscillator including a delay line varying a delay time in accordance with said digital count value.
4. A semiconductor device including plural function modules and a clock generation circuit, which supplies a clock generated therein to each of the function modules and comprises:
a frequency-multiplying circuit receiving an input of a reference clock signal and outputting a same-frequency or frequency-multiplied clock signal of said reference clock signal, said output clock signal having a logic high period and a logic low period different from each other, the difference between the logic high period and the logic low period being maintained under a predetermined level of a control signal; and
a buffering portion buffering said output clock signal, wherein
said frequency-multiplying circuit includes
a ring oscillator,
a comparator comparing a phase of said output clock signal output from said ring oscillator with a phase of said reference clock signal, and
a counter determining a digital count value based on a phase comparison result output from said comparator,
said ring oscillator including
first and second delay lines coupled in series for receiving said digital count value for determining a delay time, and
a selector selecting and outputting an input from one of said first and second delay lines in accordance with said output clock signal.
5. A semiconductor device including plural function modules and a clock generation circuit, which supplies a clock generated therein to each of the function modules and comprises:
a frequency-multiplying circuit receiving an input of a reference clock signal and outputting a same-frequency or frequency-multiplied clock signal of said reference clock signal;
a waveform generation circuit outputting a duty ratio control signal; and
an AND circuit receiving said output clock signal and said duty ratio control signal, wherein
in said duty ratio control signal, a period of time during which both of said output clock signal and said duty ratio control signal are logic high is different from the other period of time.
6. A semiconductor device including plural function modules and a clock generation circuit, which supplies a clock generated therein to each of the function modules and comprises:
a frequency-multiplying circuit receiving an input of a reference clock signal and outputting a same-frequency or frequency-multiplied clock signal of said reference clock signal;
a waveform generation circuit outputting a duty ratio control signal; and
an OR circuit receiving said output clock signal and said duty ratio control signal, wherein
in said duty ratio control signal, a period of time during which both of said output clock signal and said duty ratio control signal are logic low is different from the other period of time.
7. A semiconductor device including plural function modules and a clock generation circuit, which supplies a clock generated therein to each of the function modules and comprises:
a frequency-multiplying circuit receiving an input of a reference clock signal and outputting a same-frequency or frequency-multiplied clock signal of said reference clock signal; and
a buffering portion buffering said output clock signal, wherein
said buffering portion includes at least one buffer circuit for changing a duty ratio of said output clock signal, wherein
said buffer circuit includes
a first inverter circuit receiving said output clock signal, and
a second inverter circuit receiving an output of said first inverter circuit,
one of said first and second inverter circuits including
a plurality of first transistors coupled in parallel between a power supply node and an output node and having one polarity, a plurality of second transistors coupled in parallel between said output node and a reference node and having the other polarity, and
a driving capability control portion controlling on/off of said plurality of first and second transistors respectively using a plurality of driving capability control signals.
8. A semiconductor device including plural function modules and a clock generation circuit, which supplies a clock generated therein to each of the function modules and comprises:
a frequency-multiplying circuit receiving an input of a reference clock signal and outputting a same-frequency or frequency-multiplied clock signal of said reference clock signal; and
a buffering portion buffering said output clock signal, wherein
said buffering portion includes at least one buffer circuit for changing a duty ratio of said output clock signal, wherein
said buffer circuit includes
a first inverter circuit receiving said output clock signal,
a second inverter circuit receiving an output of said first inverter circuit, and
a timing control portion controlling rising or falling timing of a signal level output from said first inverter circuit to said second inverter circuit using a plurality of timing control signals.
9. A semiconductor device including plural function modules and a clock generation circuit, which supplies a clock generated therein to each of the function modules and comprises:
a frequency-multiplying circuit receiving an input of a reference clock signal and outputting a same-frequency or frequency-multiplied clock signal of said reference clock signal; and
a buffering portion buffering said output clock signal, wherein
said buffering portion includes at least one buffer circuit for changing a duty ratio of said output clock signal and maintaining that duty ratio of said output clock signal under a predetermined level of a first control signal, wherein
at least one of a power supply potential and a ground potential of said buffer circuit varies using a second control signal.
10. A semiconductor device including plural function modules and a clock generation circuit, which supplies a clock generated therein to each of the function modules and comprises:
a frequency-multiplying circuit receiving an input of a reference clock signal and outputting a same-frequency or frequency-multiplied clock signal of said reference clock signal; and
a buffering portion buffering said output clock signal, wherein
said buffering portion includes at least one buffer circuit for changing a duty ratio of said output clock signal and maintaining that duty ratio of said output clock signal under a predetermined level of a first control signal, wherein
a substrate potential of a transistor included in said buffer circuit varies using a second control signal.
11. A semiconductor device including plural function modules and a clock generation circuit, which supplies a clock generated therein to each of the function modules and comprises:
a frequency-multiplying circuit receiving an input of a reference clock signal and outputting a same-frequency or frequency-multiplied clock signal of said reference clock signal; and
a buffering portion buffering said output clock signal, wherein
said buffering portion includes at least one buffer circuit for changing a duty ratio of said output clock signal,
said buffer circuit comprises
a delay circuit capable of controlling a delay time using a delay control signal; and
a logic element receiving an output signal from said delay circuit and the reference clock signal for outputting a clock signal.
12. The semiconductor device according to claim 11 wherein said logic element in the clock generation circuit is an AND circuit.
13. The semiconductor device according to claim 11 wherein said logic element in the clock generation circuit is an OR circuit.
14. A semiconductor device including plural function modules and a clock generation circuit, which supplies a clock generated therein to each of the function modules and comprises:
a frequency-multiplying circuit receiving an input of a reference clock signal and outputting a same-frequency or frequency-multiplied clock signal of said reference clock signal; and
a buffering portion buffering said output clock signal, wherein
said frequency-multiplying circuit is configured for changing a duty ratio of said output clock signal, wherein
said frequency-multiplying circuit includes
a ring oscillator,
a comparator comparing a phase of said clock signal output from said ring oscillator with a phase of said reference clock signal,
a counter determining a digital count value based on a phase comparison result output from said comparator, and
a control circuit incrementing/decrementing said digital count value in accordance with a rising/falling of said reference clock signal when a count value control signal has a prescribed value,
said ring oscillator including a delay line varying a delay time in accordance with said digital count value.
15. The semiconductor device according to claim 14 wherein
whether said count value control signal takes said prescribed value is determined in accordance with said digital count value.
16. The semiconductor device according to claim 14 wherein
whether said count value control signal takes said prescribed value is determined in accordance with a frequency of said output clock signal.
17. A semiconductor device including plural function modules and a clock generation circuit, which supplies a clock generated therein to each of the function modules and comprises:
a frequency-multiplying circuit receiving an input of a reference clock signal and outputting a same-frequency or frequency-multiplied clock signal of said reference clock signal; and
a buffering portion buffering said output clock signal, wherein
said frequency-multiplying circuit is configured for changing a duty ratio of said output clock signal, wherein
said frequency-multiplying circuit includes
a ring oscillator,
a comparator comparing a phase of said output clock signal output from said ring oscillator with a phase of said reference clock signal,
a counter determining a digital count value based on a phase comparison result output from said comparator, and
a logic element receiving a selector control signal and said output clock signal for outputting a select signal,
said ring oscillator including
first and second delay lines coupled in series for receiving said digital count value for determining a delay time, and
a selector selecting and outputting an input from one of said first and second delay lines in accordance with said select signal.
18. The semiconductor device according to claim 17
wherein whether said selector control signal takes said prescribed value is determined in accordance with said digital count value.
19. The semiconductor device according to claim 17
wherein whether said selector control signal takes said prescribed value is determined in accordance with a frequency of said output clock signal.
20. A semiconductor device including plural function modules and a clock generation circuit, which supplies a clock generated therein to each of the function modules and comprises:
a frequency-multiplying circuit receiving an input of a reference clock signal and outputting a same-frequency or frequency-multiplied clock signal of said reference clock signal;
a waveform generation circuit generating a duty ratio control signal; and
an AND circuit receiving said output clock signal and said duty ratio control signal, wherein
in said duty ratio control signal, a ratio between a period of time during which both of said output clock signal and said duty ratio control signal are logic high and the other period of time varies.
21. A semiconductor device including plural function modules and a clock generation circuit, which supplies a clock generated therein to each of the function modules and comprises:
a frequency-multiplying circuit receiving an input of a reference clock signal and outputting a same-frequency or frequency-multiplied clock signal of said reference clock signal;
a waveform generation circuit generating a duty ratio control signal; and
an OR circuit receiving said output clock signal and said duty ratio control signal, wherein
in said duty ratio control signal, a ratio between a period of time during which both of said output clock signal and said duty ratio control signal are logic low and the other period of time varies.