Polar code-based decoding method and apparatus
View Patent ↗A polar code-based decoding method may comprise: converting a plurality of LLRs of calculation-target bits into a plurality of absolute (ABS) LLR values; sorting the plurality of ABS LLR values in order of size so that a minimum ABS LLR value is designated from among the plurality of ABS LLR values; multiplying the minimum ABS LLR value by a preset weight; and updating path metrics (PMs) of the calculation-target bits in an order in which the plurality of ABS LLR values are sorted, wherein the updating of the PMs of the calculation-target bits comprises, even when a specific ABS LLR value of a specific calculation-target bit is equal or similar to the minimum ABS LLR value, updating a PM of the specific calculation-target bit with the minimum ABS LLR value multiplied by the preset weight.
1 . A polar code-based decoding method performed by a single parity check (SPC) operator included in a polar code-based decoding apparatus, comprising:
converting, through a modulo operation module, a plurality of log likelihood ratios (LLRs) of calculation-target bits into a plurality of absolute (ABS) LLR values;
sorting, through a compare tree (CT), the plurality of ABS LLR values in order of size so that a minimum ABS LLR value is designated from among the plurality of ABS LLR values;
multiplying, through a shift add multiplier, the minimum ABS LLR value by a preset weight; and
updating, through at least one adder and at least one subtractor, path metrics (PMs) of the calculation-target bits in an order in which the plurality of ABS LLR values are sorted,
wherein the updating of the PMs of the calculation-target bits comprises, even when a specific ABS LLR value of a specific calculation-target bit is equal or similar to the minimum ABS LLR value, updating a PM of the specific calculation-target bit with the minimum ABS LLR value multiplied by the preset weight, and
wherein the modulo operation module, the CT, the shift add multiplier, and the at least one adder and the at least one subtractor are included in the SPC operator.
2 . The polar code-based decoding method of claim 1 , further comprising maintaining the minimum ABS LLR value for a certain time period corresponding to a calculation time of the calculation-target bits or for a preset number of PM updates.
3 . The polar code-based decoding method of claim 1 , wherein the preset weight is 0.75.
4 . The polar code-based decoding method of claim 1 , further comprising obtaining a parity value by performing an exclusive OR (XOR) operation on hard decision (HD) results of the plurality of LLRs.
5 . The polar code-based decoding method of claim 4 , wherein the updating of the PMs of the calculation-target bits comprises adding or subtracting the minimum ABS LLR value multiplied by the preset weight to or from a current ABS LLR value of a current calculation-target bit according to the parity value.
6 . The polar code-based decoding method of claim 5 , wherein the updating of the PMs of the calculation-target bits further comprises adding a previous PM and a value obtained by adding or subtracting the minimum ABS LLR value multiplied by the preset weight to or from the current ABS LLR value.
7 . The polar code-based decoding method of claim 5 , further comprising outputting two PMs which are obtained by duplicating a previous PM and a value obtained by adding or subtracting the minimum ABS LLR value multiplied by the preset weight to or from the current ABS LLR value as a first current PM corresponding to a probability for 0 and a second current PM corresponding to a probability for 1.
8 . A polar code-based decoding method, performed by a decoding apparatus including a processor and a pruning processing unit having a single parity check (SPC) operator, comprising:
setting, by the processor, a number of path splittings to a smaller value of a list size and a node size of a decoding tree to which a successive cancellation list (SCL) algorithm is applied;
comparing, by the processor, a position of a current calculation-target bit with the smaller value;
performing, by the SPC operator, path splitting when it is determined that the position of the current calculation-target bit is smaller than the smaller value; and
making, through a hard decision (HD) module, a hard decision when it is determined that the position of the current calculation-target bit is not smaller than the smaller value,
wherein the SPC operator performs the path splitting by:
converting, through a modulo operation module, a plurality of log likelihood ratios (LLRs) of calculation-target bits into a plurality of absolute (ABS) LLR values;
sorting, through a compare tree (CT), the plurality of ABS LLR values in order of size so that a minimum ABS LLR value is designated from among the plurality of ABS LLR values;
multiplying, through a shift add multiplier, the minimum ABS LLR value by a preset weight; and
updating, through at least one adder and at least one subtractor, path metrics (PMs) of the calculation-target bits in the order in which the plurality of ABS LLR values are sorted,
wherein the updating of the PMs of the calculation-target bits comprises, even when a specific ABS LLR value of a specific calculation-target bit is equal or similar to the minimum ABS LLR value, updating a PM of the specific calculation-target bit with the minimum ABS LLR value multiplied by the preset weight.
9 . The polar code-based decoding method of claim 8 , further comprising initializing the PMs to decode the calculation-target bits.
10 . The polar code-based decoding method of claim 9 , further comprising:
determining whether the position of the current calculation-target bit is smaller than the node size; and
when the position of the calculation-target bit is smaller than the node size, returning to the comparing of the current calculation-target bit with the smaller value to perform path splitting or make an HD repeatedly until the position of the current calculation-target bit is not smaller than the node size.
11 . The polar code-based decoding method of claim 10 , further comprising verifying decoding results of the calculation-target bits including one pair of PMs obtained by updating a PM of each of the calculation-target bits under an even-parity constraint.
12 . A polar code-based decoding apparatus comprising a processor configured to decode a message according to a program or command stored in a memory and a single parity check (SPC) operator,
wherein the processor performs operations of:
converting, through a modulo operation module included in the SPC operator, a plurality of log likelihood ratios (LLRs) of calculation-target bits into a plurality of absolute (ABS) LLR values;
sorting, through a compare tree (CT) included in the SPC operator, the plurality of ABS LLR values in order of size so that a minimum ABS LLR value is designated from among the plurality of ABS LLR values;
multiplying, through a shift add multiplier included in the SPC operator, the minimum ABS LLR value by a preset weight; and
updating, through at least one adder and at least one subtractor included in the SPC operator, path metrics (PMs) of the calculation-target bits in the order in which the plurality of ABS LLR values are sorted,
wherein, in the operation of updating the PMs of the calculation-target bits, even when a specific ABS LLR value of a specific calculation-target bit is equal or similar to the minimum ABS LLR value, the processor updates a PM of the specific calculation-target bit with the minimum ABS LLR value multiplied by the preset weight.
13 . The polar code-based decoding apparatus of claim 12 , wherein the processor further performs an operation of maintaining the minimum ABS LLR value for a certain time period corresponding to a calculation time of the calculation-target bits or for a preset number of PM updates.
14 . The polar code-based decoding apparatus of claim 12 , wherein the preset weight is 0.75.
15 . The polar code-based decoding apparatus of claim 12 , wherein the processor further performs an operation of obtaining a parity value by performing an exclusive OR (XOR) operation on hard decision (HD) results of the plurality of LLRs.
16 . The polar code-based decoding apparatus of claim 15 , wherein, in the operation of updating the PMs of the calculation-target bits, the processor adds or subtracts the minimum ABS LLR value multiplied by the preset weight to or from a current ABS LLR value of a current calculation-target bit according to the parity value.
17 . The polar code-based decoding apparatus of claim 16 , wherein, in the operation of updating the PMs of the calculation-target bits, the processor adds a previous PM and a value obtained by adding or subtracting the minimum ABS LLR value multiplied by the preset weight to or from the current ABS LLR value.
18 . The polar code-based decoding apparatus of claim 16 , wherein the processor further performs an operation of outputting two PMs which are obtained by duplicating a previous PM and a value obtained by adding or subtracting the minimum ABS LLR value multiplied by the preset weight to or from the current ABS LLR value as a first current PM corresponding to a probability for 0 and a second current PM corresponding to a probability for 1.