Method and apparatus for generating a decoding position control signal for decoding using polar codes

1. A method for generating a decoding position control signal for decoding using polar codes by an apparatus for generating the decoding position control signal for decoding using the polar codes, the method comprising:

generating a decoding tree obtained by forming a plurality of nodes in a hierarchical structure for a polar-encoded codeword;

decoding the codeword using a successive cancellation (SC) decoding technique;

generating a control signal through a preset operation relationship based on a position of a bit returned during re-decoding among the decoded codeword; and

performing re-decoding at the position of the bit returned during re-decoding based on the control signal,

wherein the generating of the control signal comprises generating the control signal based on a first bit string indicating the position of the bit returned during the re-decoding, and a second bit string calculated through the preset operation relationship with the first bit string,

wherein the first bit string and the second bit string are expressed in a binary system having a log 2 N number of bit places (where N is a codeword length of the codeword),

wherein the apparatus further includes an adder and an exclusive-OR (XOR) operator, and

wherein in the preset operation relationship, the second bit string is output by adding the first bit string and 2's complement of 1 using the adder, and performing an exclusive-OR operation of the first bit string and a result of the addition using the XOR operator.

2. The method of claim 1 , wherein

in the decoding of the codeword, nodes of the lowest stage are sequentially decoded one by one by searching the nodes of the lowest stage from a node of the highest stage in the decoding tree in a depth-first search (DFS) method.

3. The method of claim 1 , wherein

the performing further includes:

generating clock cycle information required to decode the bit returned during the re-decoding through the number of is in all bit places in the second bit string;

generating stage information in which an operation to be performed through a bit place value of the second bit string; and

generating operation information performed through the stage information through a bit place value of the first bit string.

4. The method of claim 3 , wherein

in the generating of the stage information,

it is checked whether or not the operation is to be performed in a j-th stage of the decoding tree through a j-th bit place of the second bit string, and when a j-th bit place value of the second bit string is 1, it is determined that the operation is to be performed in the j-th stage of the decoding tree (where j is from (log 2 N−1) to 0 in descending order from left).

5. The method of claim 4 , wherein

in the generating of the operation information,

the operation to be performed in the j-th stage in which the operation is determined to be performed is checked through a j-th bit place of the first bit string, and if a bit place value of the first bit string is 0, the operation to be performed in the j-th stage is determined as an f operation, and if the j-th bit place value of the first bit string is 1, the operation to be performed in the j-th stage is determined as a g operation.

6. An apparatus for generating a decoding position control signal for decoding using polar codes, the apparatus comprising:

a processor; and

a memory storing instructions executable by the processor;

wherein the processor is configured to:

generate a decoding tree obtained by forming a plurality of nodes in a hierarchical structure for a polar-encoded codeword;

decode the codeword using a successive cancellation (SC) decoding technique;

generate a control signal through a preset operation relationship based on a position of a bit returned during re-decoding among the decoded codeword; and

wherein the processor is further configured to:

perform re-decoding at the position of the bit returned during re-decoding based on the control signal, and

generate the control signal based on a first bit string indicating the position of the bit returned during the re-decoding, and a second bit string calculated through the preset operation relationship with the first bit string,

wherein the first bit string and the second bit string are expressed in a binary system having a log 2 N number of bit places (where N is a codeword length of the codeword),

wherein the apparatus further comprises an adder and an exclusive-OR (XOR) operator, and

wherein in the preset operation relationship, the second bit string is output by adding the first bit string and 2's complement of 1 using the adder, and performing an exclusive-OR operation of the first bit string and a result of the addition using the XOR operator.

7. The apparatus of claim 6 , wherein

the processor is further configured to sequentially decode nodes of the lowest stage one by one by searching the nodes of the lowest stage from a node of the highest stage in the decoding tree in a depth-first search (DFS) method.

8. The apparatus of claim 6 , wherein

the processor is further configured to generate clock cycle information required to decode the bit returned during the re-decoding through the number of 1s in bit places in the second bit string, generate stage information (=information of a stage) in which an operation to be performed through a bit place value of the second bit string, and generate operation information to be performed through the stage information through a bit place value of the first bit string.

9. The apparatus of claim 8 , wherein

the processor is further configured to check whether or not the operation is to be performed in a j-th stage of the decoding tree through a j-th bit place of the second bit string, and generate the stage information by determining that the operation is to be performed in the j-th stage of the decoding tree when a j-th bit place value of the second bit string is 1 (where j is from (log 2 N−1) to 0 in descending order from left).

10. The apparatus of claim 9 , wherein

the processor is further configured to check the operation to be performed in the j-th stage in which the operation is determined to be performed through a j-th bit place of the first bit string, and generate the stage information by determining that the operation to be performed in the j-th stage as an f operation if a bit place value of the first bit string is 0, and by determining that the operation to be performed in the j-th stage as a g operation if the j-th bit place value of the first bit string is 1.