IP Library › Granted Patent US 12,525,561
Granted Patent B2
US 12,525,561 · App. 18/459,196 · Granted Jan 13, 2026

Semiconductor device and method of forming dummy SOP within saw street

Inventors: KyuWon Lee (Gyeonggi-do, KR); JiWon Jang (Seoul, KR); Myeongjin Kim (Incheon, KR); HyeSun Kim (Incheon, KR); YoungDeuk Lee (Seoul, KR); YoungJin Woo (Gyeonggi-do, KR)
Assignee: STATS ChipPAC Pte. Ltd.
H01L24/14H01L24/97H01L2224/14131H01L2224/14515H01L2224/97
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,525,561
App. No.
18/459,196
Granted
Jan 13, 2026
Kind
B2
Abstract

A semiconductor device has a semiconductor wafer or substrate including a plurality of semiconductor die. A plurality of first bumps is formed over an active surface of the semiconductor wafer. A plurality of second bumps is formed within a saw street of the semiconductor wafer separating the plurality of semiconductor die. A top surface of the first bumps is coplanar with a top surface of the second bumps. The second bumps are formed within a first saw street of the semiconductor wafer and further within a second saw street of the semiconductor wafer different from the first saw street. The first bumps are electrically connected to the semiconductor die to provide a function for the semiconductor die. The second bumps are dummy bumps that have no electrical function for the semiconductor die. The semiconductor wafer is singulated through the saw street and second bumps.

Claims (37)

1 . A semiconductor device, comprising:

a semiconductor wafer or substrate including a plurality of semiconductor die;

a plurality of first bumps formed over an active surface of the semiconductor wafer or substrate; and

a plurality of second bumps formed within a saw street of the semiconductor wafer or substrate separating the plurality of semiconductor die.

2 . The semiconductor device of claim 1 , wherein a top surface of the first bumps is coplanar with a top surface of the second bumps.

3 . The semiconductor device of claim 1 , wherein the plurality of second bumps is formed within a first saw street of the semiconductor wafer or substrate.

4 . The semiconductor device of claim 3 , wherein the plurality of second bumps is formed within a second saw street of the semiconductor wafer or substrate different from the first saw street.

5 . The semiconductor device of claim 1 , wherein the first bumps are electrically connected to the semiconductor die to provide a function for the semiconductor die.

6 . The semiconductor device of claim 1 , wherein the second bumps are dummy bumps have no electrical function for the semiconductor die.

7 . A semiconductor device, comprising:

a semiconductor wafer or substrate;

a plurality of first bumps formed over an active surface of the semiconductor wafer or substrate; and

a plurality of second bumps formed within a saw street of the semiconductor wafer or substrate.

8 . The semiconductor device of claim 7 , wherein the semiconductor wafer or substrate includes a plurality of semiconductor die.

9 . The semiconductor device of claim 8 , wherein the first bumps are electrically connected to the semiconductor die to provide a function for the semiconductor die.

10 . The semiconductor device of claim 8 , wherein the second bumps are dummy bumps that have no electrical function for the semiconductor die.

11 . The semiconductor device of claim 7 , wherein a top surface of the first bumps is coplanar with a top surface of the second bumps.

12 . The semiconductor device of claim 7 , wherein the plurality of second bumps is formed within a first saw street of the semiconductor wafer or substrate.

13 . The semiconductor device of claim 12 , wherein the plurality of second bumps is formed within a second saw street of the semiconductor wafer or substrate different from the first saw street.

14 . A method of making a semiconductor device, comprising:

providing a semiconductor wafer or substrate including a plurality of semiconductor die;

forming a plurality of first bumps over an active surface of the semiconductor wafer or substrate; and

forming a plurality of second bumps within a saw street of the semiconductor wafer or substrate separating the plurality of semiconductor die.

15 . The method of claim 14 , wherein a top surface of the first bumps is coplanar with a top surface of the second bumps.

16 . The method of claim 14 , wherein the plurality of second bumps is formed within a first saw street of the semiconductor wafer or substrate.

17 . The method of claim 16 , wherein the plurality of second bumps is formed within a second saw street of the semiconductor wafer or substrate different from the first saw street.

18 . The method of claim 14 , wherein the first bumps are electrically connected to the semiconductor die to provide a function for the semiconductor die, and the second bumps are dummy bumps that have no electrical function for the semiconductor die.

19 . The method of claim 14 , further including singulating the semiconductor wafer or substrate through the saw street and second bumps.

20 . A method of making a semiconductor device, comprising:

providing a semiconductor wafer or substrate;

forming a plurality of first bumps over an active surface of the semiconductor wafer or substrate; and

forming a plurality of second bumps within a saw street of the semiconductor wafer or substrate.

21 . The method of claim 20 , wherein the semiconductor wafer or substrate includes a plurality of semiconductor die.

22 . The method of claim 21 , wherein the first bumps are electrically connected to the semiconductor die to provide a function for the semiconductor die, and the second bumps are dummy bumps that have no electrical function for the semiconductor die.

23 . The method of claim 20 , wherein a top surface of the first bumps is coplanar with a top surface of the second bumps.

24 . The method of claim 20 , wherein the plurality of second bumps is formed within a first saw street of the semiconductor wafer or substrate and further formed within a second saw street of the semiconductor wafer or substrate different from the first saw street.

25 . The method of claim 20 , further including singulating the semiconductor wafer or substrate through the saw street and second bumps.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2023
From: LEE, KYUWON; JANG, JIWON; KIM, MYEONGJIN; KIM, HYESUN; LEE, YOUNGDEUK; WOO, YOUNGJIN
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064768/0523 →
Continuity (1)
Related Publication 20250079372A1 · Mar 6, 2025
References Cited (10)
US 7061117B2 · Yang et al. · 2006 [cited by applicant]
US 8574960B2 · Pagaila · 2013 [cited by examiner]
US 9343429B2 · Pagaila · 2016 [cited by examiner]
US 10504751B2 · Chen · 2019 [cited by examiner]
US 10665534B2 · Lee · 2020 [cited by examiner]
US 11682646B2 · Nayini et al. · 2023 [cited by applicant]
US 20140264905A1 · Lee · 2014 [cited by examiner]
US 20150001709A1 · Bao · 2015 [cited by examiner]
US 20210066239A1 · Moreno · 2021 [cited by examiner]
US 20230253271A1 · Blin · 2023 [cited by examiner]