High voltage semiconductor device and manufacturing method of high voltage semiconductor device
A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.
1. A method of manufacturing a semiconductor device, the method comprising:
forming a first buried layer in a substrate;
forming a second buried layer spaced apart from the first buried layer;
forming a drift region and a body region with different conductivity types on the second buried layer;
forming a gate electrode on the drift region and the body region;
forming a source region in the body region and a drain region in the drift region;
forming a non-silicide layer between the gate electrode and the drain region, the non-silicide layer being insulative and extending to an upper surface of the gate electrode;
forming a silicide layer on the gate electrode;
forming an interlayer insulating layer on the non-silicide layer and the silicide layer;
forming a field plate plug in the interlayer insulating film to overlap the non-silicide layer; and
forming a metal layer on the interlayer insulating layer,
wherein the second buried layer has a conductivity type opposite to that of the first buried layer and has a length smaller than a length of the first buried layer.
2. The method of claim 1 , further comprising:
forming a deep well region on the first buried layer; and
forming an etch stopping layer on the non-silicide layer and the silicide layer,
wherein the deep well region has a same conductivity type as the second buried layer.
3. The method of claim 1 , further comprising:
forming a source contact plug on the source region;
forming a drain contact plug on the drain region; and
forming a gate contact plug on the gate electrode,
wherein the field plate plug is electrically connected to one or both of the source contact plug and the gate contact plug.
4. The method of claim 1 , wherein the second buried layer has a length greater than a length of the drift region.
5. The method of claim 1 , wherein the non-silicide layer comprises:
a first insulating film; and
a second insulating film on the first insulating film and having a material different from a material of the first insulating film.
6. The method of claim 5 , wherein the first insulating film has a length equal to a length of the second insulating film, and both ends of the first insulating film are aligned with both ends of the second insulating film.
7. The method of claim 1 , further comprising:
forming a spacer on a sidewall of the gate electrode,
wherein the non-silicide layer is formed on the gate electrode, the spacer and the drift region.
8. The method of claim 3 , wherein the field plate plug has a bottom surface that is lower than a bottom surface of the gate contact plug and higher than a bottom surface of the source contact plug and the drain contact plug.
9. A method of manufacturing a semiconductor device, the method comprising:
forming a first buried layer in a substrate;
forming a deep well region on the first buried layer;
forming a second buried layer spaced apart from the first buried layer;
forming a drift region and a body region with different conductivity types on the second buried layer;
forming a gate electrode on the drift region and the body region;
forming a source region in the body region and a drain region in the drift region;
forming a non-silicide layer between the gate electrode and the drain region, the non-silicide layer being insulative and extending to an upper surface of the gate electrode;
forming a silicide layer on the gate electrode;
forming an etch stopping layer on the non-silicide layer and the silicide layer;
forming an interlayer insulating layer on the etch stopping layer formed on the non-silicide layer and the silicide layer;
forming a field plate plug in the interlayer insulating film to overlap the non-silicide layer; and
forming a metal layer on the interlayer insulating layer,
wherein the deep well region has a same conductivity type as the second buried layer.
10. The method of claim 9 , wherein the second buried layer has a conductivity type opposite to that of the first buried layer and has a length smaller than a length of the first buried layer.
11. The method of claim 9 , further comprising:
forming a spacer on a sidewall of the gate electrode,
wherein the non-silicide layer is formed on the gate electrode, the spacer and the drift region.
12. The method of claim 9 , further comprising:
forming a source contact plug on the source region;
forming a drain contact plug on the drain region; and
forming a gate contact plug on the gate electrode,
wherein the field plate plug has a bottom surface that is lower than a bottom surface of the gate contact plug and higher than a bottom surface of the source contact plug and the drain contact plug.