IP Library › Granted Patent US 12,733,237
Granted Patent B2
US 12,733,237 · App. 18/466,432 · Granted Sep 8, 2026

Semiconductor device and method

Inventors: Thomas Ralf Siemieniec (Villach, AT); Oliver Blank (Villach, AT)
Assignee: Infineon Technologies Austria AG
H10D64/117H10D12/038H10D12/481H10D30/0297H10D30/668
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,733,237
App. No.
18/466,432
Granted
Sep 8, 2026
Kind
B2
Abstract

A semiconductor device includes: a semiconductor substrate having a first major surface; a trench extending from the first major surface into the semiconductor substrate and having a base and a side wall extending from the base to the first major surface; a field plate arranged in the trench and having a height f; and a dielectric structure arranged between the semiconductor body and the field plate. The dielectric structure includes a first portion having a first dielectric constant and a second portion having a second dielectric constant that is higher than the first dielectric constant, the first portion being arranged in a lower portion of the trench and the second portion being arranged in an upper portion of the trench. The second portion of the dielectric structure overlaps the height of the field plate by a distance vi, where f*0.1≤vi≤f* 0.8.

Claims (49)

1 . A semiconductor device, comprising:

a semiconductor substrate having a first major surface;

a trench extending from the first major surface into the semiconductor substrate and having a base and a side wall extending from the base to the first major surface;

a field plate arranged in the trench and having a height f; and

a dielectric structure arranged between the semiconductor body and the field plate,

wherein the dielectric structure comprises a first portion comprising a first dielectric constant and a second portion comprising a second dielectric constant that is higher than the first dielectric constant,

wherein the first portion of the dielectric structure is arranged in a lower portion of the trench and the second portion of the dielectric structure is arranged in an upper portion of the trench,

wherein the second portion of the dielectric structure overlaps the height of the field plate by a distance v 1 ,

wherein f*0.1≤v 1 ≤f*0.8.

2 . The semiconductor device of claim 1 , wherein the first portion of the dielectric structure is formed of an oxide and the second portion of the dielectric structure is formed of a high K material.

3 . The semiconductor device of claim 1 , wherein the first portion of the dielectric structure comprises an enclosed cavity that is laterally positioned between a side wall of the field plate and the side wall of the trench and the second portion of the dielectric structure provides a cap that seals the cavity.

4 . The semiconductor device of claim 1 , wherein the semiconductor device is a transistor device, wherein the semiconductor substrate comprises a drift region of the first conductivity type, a body region of the second conductivity type that opposes the first conductivity type arranged on and forming a pn junction with the drift region, and a source region of the first conductivity type on and/or in the body region, wherein the pn junction is located at a depth d from the first major surface and the second portion vertically overlaps the drift region by a distance v 2 .

5 . The semiconductor device of claim 4 , wherein d*0.1≤v 2 ≤d*0.8 or d*0.3≤v 2 ≤d*0.6.

6 . The semiconductor device of claim 4 , wherein f*0.1≤v 2 ≤f*0.8 or f*0.3≤v 2 ≤f*0.6.

7 . The semiconductor device of claim 1 , wherein the field plate has a lower surface, and wherein the lower surface of the field plate is spaced apart from the base of a trench by a pillar of dielectric material having a height a.

8 . The semiconductor device of claim 7 , wherein the first portion of the dielectric structure has a base that vertically overlaps with the pillar by a distance b, and wherein b≥a*0.6 or b≥a*0.8.

9 . The semiconductor device of claim 1 , wherein the field plate and the side wall and the base of the trench are covered with a dielectric layer, and wherein the cavity comprises a base and sidewalls formed by the dielectric layer.

10 . The semiconductor device of claim 1 , wherein f*0.3≤v 1 ≤f*0.6.

11 . A method, comprising:

forming a trench in a first major surface of a semiconductor substrate, the trench having a base and a side wall extending from the base to the first major surface;

forming a first insulating layer on the base and the side wall of the trench;

inserting conductive material into the trench and filling the trench;

selectively removing the first insulation layer from the side wall and peripheral regions of the base of the trench to form a recess;

after selectively removing the first insulation layer from the side wall and the peripheral regions of the base of the trench to form the recess, forming a third insulating layer over a surface of a field plate formed from the conductive material in the trench, the side wall of the trench, and the peripheral regions of the base of the trench; and

forming a second insulating layer in the trench, wherein the second insulating layer forms a cap that caps the recess to form an enclosed cavity in the trench.

12 . The method of claim 11 , wherein forming the first insulating layer comprises:

forming a first insulating sublayer on the side wall and the base of the trench;

removing the first insulating sublayer at least from the side wall of the trench such that the first insulating sublayer remains on the base of the trench; and

forming a second insulating sublayer on the sidewall of the trench.

13 . The method of claim 12 , wherein the first insulating layer is further formed over the first major surface of the substrate, wherein the conductive material is further formed over the first insulating layer formed on the first major surface of the substate, the method further comprising:

subsequently carrying out a planarization process.

14 . The method of claim 13 , wherein the planarization process comprises selectively plasma etching the conductive material, or chemical mechanical polishing the conductive material followed by plasma etching to remove the first insulating layer, or chemical mechanical polishing to remove the conductive material and the first insulating layer.

15 . The method of claim 12 , wherein:

the first insulating sublayer is formed by high density plasma deposition; and/or

the first insulating sublayer is removed from the side wall of the trench by wet etching; and/or

the second insulating sublayer is formed by atomic layer deposition; and/or

the first insulating layer is removed by wet etching or plasma etching, or wet etching followed by plasma etching; and/or

the second insulating layer is formed by atomic layer deposition or chemical vapour deposition or TEOS deposition.

16 . The method of claim 12 , wherein:

the cap has a thickness x, the field plate has a height f, the cap overlaps the field plate by a distance v 1 , and f*0.1≤v 1 ≤f*0.8 or f*0.3≤v 1 ≤f*0.6; and/or

a pillar spaces the field plate spaced apart from the base of a trench by a height a, the cavity has a base that vertically overlaps with the pillar by a distance b, and b≥a*0.6 or b≥a*0.8.

17 . The method of claim 11 , wherein forming the first insulating layer comprises:

forming a first insulating sublayer on the side wall and the base of the trench;

filling the trench with a sacrificial material;

selectively removing the sacrificial material from an upper portion of the trench to form a recess with a plug of sacrificial material at a base of the recess;

removing the first insulating sublayer from the side wall of the trench such that the first insulating sublayer remains on the base of the trench and the plug protrudes above the first insulating sublayer remaining on the base of the trench;

removing the plug; and

forming a second insulating sublayer on the sidewall of the trench and on the first insulating sublayer remaining on the base of the trench.

18 . The method of claim 11 , wherein while the second insulating layer is being formed in the trench to cap the recess and form the enclosed cavity in the trench, the second insulating layer is further formed on the peripheral regions of the base of the trench.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2023
From: BLANK, OLIVER; SIEMIENIEC, THOMAS RALF
To: INFINEON TECHNOLOGIES AUSTRIA AG
Reel/Frame 064892/0620 →
Priority Claims (1)
EP 22198238 · Sep 28, 2022 · regional
Continuity (1)
Related Publication 20240105784A1 · Mar 28, 2024
References Cited (8)
US 10304933B1 · Woo et al. · 2019 [cited by applicant]
US 20170263767A1 · Nishiwaki · 2017 [cited by applicant]
US 20170330943A1 · Haase et al. · 2017 [cited by applicant]
US 20200083335A1 · Leomant · 2020 [cited by examiner]
US 20220231136A1 · Leomant · 2022 [cited by examiner]
US 20230163210A1 · Ma · 2023 [cited by examiner]
CN 106298939A · 2017 [cited by applicant]
WO 2012006261A2 · 2012 [cited by applicant]