Two-dimensional vertical fins
View Patent ↗A method of forming a two dimensional (2D) vertical fin is provided. The method includes heat treating a periodic array of irregular openings in a substrate, wherein there are walls of substrate material between adjacent openings, to reduce the surface area of the openings, and etching the openings with a crystal-plane selective etch to form squared openings in the substrate.
1. A two-dimensional vertical fin field effect transistor device, comprising:
a two-dimensional vertical fin;
an extension region having a same shape as the two-dimensional vertical fin between the two-dimensional vertical fin and a substrate; and
a top source/drain on the two-dimensional vertical fin, wherein a top surface of the top source/drain region on the two-dimensional vertical fin has a cross shape.
2. The two-dimensional vertical fin field effect transistor device of claim 1 , further comprising a bottom source/drain extending beyond edges of the extension region, wherein the bottom source/drain is located at a rectangular region in the substrate.
3. The two-dimensional vertical fin field effect transistor device of claim 2 , further comprising a bottom spacer layer directly on the bottom source/drain and laterally adjacent to the extension region.
4. The two-dimensional vertical fin field effect transistor device of claim 3 , further comprising a top spacer layer laterally adjacent to the top source/drain.
5. The two-dimensional vertical fin field effect transistor device of claim 4 , further comprising a gate dielectric layer directly on a sidewall of the two-dimensional vertical fin, wherein the gate dielectric layer is between the top spacer layer and the bottom spacer layer, and a conductive gate fill on the bottom spacer layer and gate dielectric layer.
6. The two-dimensional vertical fin field effect transistor device of claim 1 , wherein the top source/drain has the same shape as the two-dimensional vertical fin.
7. A two-dimensional vertical fin field effect transistor device, comprising:
a two-dimensional vertical fin;
an extension region having a same shape as the two-dimensional vertical fin between the two-dimensional vertical fin and a substrate;
a top source/drain region on the two-dimensional vertical fin, having a same shape as the two-dimensional vertical fin, wherein a top surface of the top source/drain region on the two-dimensional vertical fin has an H-shape; and
a bottom spacer layer directly on a bottom source/drain and laterally adjacent to the extension region.
8. The two-dimensional vertical fin field effect transistor device of claim 7 , wherein the bottom source/drain extends beyond edges of the extension region and is located at a rectangular region in the substrate.
9. The two-dimensional vertical fin field effect transistor device of claim 7 , further comprising a top spacer layer laterally adjacent to the top source/drain region.
10. The two-dimensional vertical fin field effect transistor device of claim 9 , further comprising a gate dielectric layer directly on a sidewall of the two-dimensional vertical fin, wherein the gate dielectric layer is between the top spacer layer and the bottom spacer layer, and a conductive gate fill on the bottom spacer layer and gate dielectric layer.
11. A two-dimensional vertical fin field effect transistor device, comprising:
a two-dimensional vertical fin;
an extension region having a same shape as the two-dimensional vertical fin between the two-dimensional vertical fin and a substrate; and
a top source/drain region on the two-dimensional vertical fin, wherein a top surface of the top source/drain region on the two-dimensional vertical fin has a shape selected from the group consisting of a fence shape and a lattice shape.
12. The two-dimensional vertical fin field effect transistor device of claim 11 , further comprising a bottom source/drain extending beyond edges of the extension region, wherein the bottom source/drain is located at a rectangular region in the substrate.
13. The two-dimensional vertical fin field effect transistor device of claim 11 , wherein the top source/drain region has the same shape as the two-dimensional vertical fin.
14. The two-dimensional vertical fin field effect transistor device of claim 13 , further comprising a bottom spacer layer directly on a bottom source/drain and laterally adjacent to the extension region.
15. The two-dimensional vertical fin field effect transistor device of claim 14 , further comprising a top spacer layer laterally adjacent to the top source/drain region.
16. The two-dimensional vertical fin field effect transistor device of claim 15 , further comprising a gate dielectric layer directly on a sidewall of the two-dimensional vertical fin.
17. The two-dimensional vertical field effect transistor device of claim 16 , wherein the gate dielectric layer is between the top spacer layer and the bottom spacer layer.
18. The two-dimensional vertical field effect transistor device of claim 17 , wherein a conductive gate fill is present on the bottom spacer layer and gate dielectric layer.