Dynamic configuration of an oscillator using adaptive voltage and code scaling to follow a target frequency

1 . A method for adaptive voltage scaling, comprising:

generating a voltage adjustment signal based on a hint from a frequency-locked loop (FLL), wherein the FLL includes an oscillator that generates a clock signal at a clock frequency;

sending the voltage adjustment signal to a power management unit (PMU) to cause the PMU to supply an adjusted operating voltage to the FLL;

obtaining a minimum code set from a minimum code table according to the adjusted operating voltage and an operating temperature; and

determining a code by the FLL from the minimum code set, wherein the clock frequency of the oscillator is generated to match a target frequency according to the code and the adjusted operating voltage, and wherein obtaining the minimum code set further comprises:

identifying, from the minimum code table, first fine codes at a first voltage level above the adjusted operating voltage and second fine codes at a second voltage level below the adjusted operating voltage; and

obtaining fine codes in the minimum code set at the adjusted operating voltage by interpolating between the first fine codes and the second fine codes.

2 . The method of claim 1 , wherein the voltage adjustment signal indicates an increase by a step size or a decrease by the step size in a present operating voltage of the FLL.

3 . The method of claim 1 , wherein the voltage adjustment signal is generated at a predetermined time interval for the PMU to periodically adjust voltage supplied to the FLL.

4 . The method of claim 1 , further comprising:

updating a dynamic voltage-frequency table to indicate that the adjusted operating voltage corresponds to the clock frequency.

5 . The method of claim 4 , wherein the dynamic voltage-frequency table is updated at a predetermined time interval during operation of the FLL.

6 . The method of claim 1 , wherein the minimum code set is updated at a predetermined time interval during operation of the FLL.

7 . The method of claim 1 , wherein the minimum code set includes a plurality of fine codes and corresponding coarse codes, the method further comprises:

determining a fine code in the minimum code set based on the adjusted operating voltage, an operating temperature, and a corresponding coarse code.

8 . The method of claim 1 , wherein the minimum code set includes a plurality of fine codes, the method further comprises:

calculating a code margin based on an operating temperature; and

adding the code margin to the fine codes that correspond to the adjusted operating voltage.

9 . The method of claim 1 , further comprising:

dynamically adjusting the code provided to the oscillator to control the clock frequency at the adjusted operating voltage.

10 . A system operative to perform adaptive voltage scaling, comprising:

a frequency-locked loop (FLL) circuit including an oscillator, the oscillator operative to generate a clock signal at a clock frequency; and

a circuit operative to control dynamic voltage and code scaling (DVCS), the circuit is further operative to:

generate a voltage adjustment signal based on a hint from the FLL;

send the voltage adjustment signal to a power management unit (PMU) to cause the PMU to supply an adjusted operating voltage to the FLL;

obtain a minimum code set from a minimum code table according to the adjusted operating voltage and an operating temperature; and

determine a code by the FLL from the minimum code set, wherein the clock frequency of the oscillator is generated to match a target frequency according to the code and the adjusted operating voltage, and wherein when obtaining the minimum code set, the circuit is further operative to:

identify, from the minimum code table, first fine codes at a first voltage level above the adjusted operating voltage and second fine codes at a second voltage level below the adjusted operating voltage; and

obtain fine codes in the minimum code set at the adjusted operating voltage by interpolating between the first fine codes and the second fine codes.

11 . The system of claim 10 , wherein the voltage adjustment signal indicates an increase by a step size or a decrease by the step size in a present operating voltage of the FLL.

12 . The system of claim 10 , wherein the voltage adjustment signal is generated at a predetermined time interval for the PMU to periodically adjust voltage supplied to the FLL.

13 . The system of claim 10 , wherein the circuit is further operative to:

update a dynamic voltage-frequency table to indicate that the adjusted operating voltage corresponds to the clock frequency.

14 . The system of claim 13 , wherein the dynamic voltage-frequency table is updated at a predetermined time interval during operation of the FLL.

15 . The system of claim 10 , wherein the minimum code set is updated at a predetermined time interval during operation of the FLL.

16 . The system of claim 10 , wherein the minimum code set includes a plurality of fine codes and corresponding coarse codes, the circuit is further operative to:

determine a fine code in the minimum code set based on the adjusted operating voltage, an operating temperature, and a corresponding coarse code.

17 . The system of claim 10 , wherein the minimum code set includes a plurality of fine codes, the circuit is further operative to:

calculate a code margin based on an operating temperature; and

add the code margin to the fine codes that correspond to the adjusted operating voltage.

18 . The system of claim 10 , wherein the circuit is further operative to:

dynamically adjust the code provided to the oscillator to control the clock frequency at the adjusted operating voltage.