Apparatus, system, and method for controlling temperature and power supply voltage drift in a digital phase locked loop
Described herein are apparatus, system, and method for controlling temperature drift and/or voltage supply drift in a digital phase locked loop (DPLL). The apparatus comprises a DPLL including a digital filter to generate a fine code for controlling a frequency of an output signal of a digital controlled oscillator (DCO) of the DPLL; a logic unit to monitor the fine code and to generate a compensation signal based on the fine code; and a voltage adjustment unit to update a power supply level to the DCO based on the compensation signal, wherein the updated power supply level to cause the digital filter to generate the fine code near the middle of an entire range of the fine code across various temperatures, and wherein the digital filter to generate the fine code near the middle of the entire range across power supply drift.
1. An apparatus comprising:
a digital phase locked loop (DPLL) including a digital filter to generate a fine code for controlling a frequency of an output signal of a digital controlled oscillator (DCO) of the DPLL, the DCO being supplied a power supply level;
a logic unit to monitor the fine code and to generate a compensation signal based on the fine code; and
a voltage adjustment unit to update the power supply level based on the compensation signal.
2. The apparatus of claim 1 , wherein the compensation signal is a temperature compensation signal, and wherein the updated power supply level to cause the digital filter to generate the fine code to be near the middle of an entire range of the fine code across various temperatures.
3. The apparatus of claim 1 , wherein the voltage adjustment unit comprises:
an adjustable reference voltage generator to generate a reference voltage according to the compensation signal; and
a voltage regulator to generate the updated power supply level for the DCO, the updated power supply level based on the reference voltage.
4. The apparatus of claim 3 , wherein the adjustable reference voltage generator comprises a bandgap reference generator.
5. The apparatus of claim 3 , wherein the adjustable reference voltage generator comprises a resistor divider network.
6. The apparatus of claim 3 further comprises:
a low pass filter (LPF) coupled to the adjustable reference voltage generator and the voltage adjustment unit, the LPF to filter the reference voltage.
7. The apparatus of claim 1 , wherein the logic unit comprises:
a register to store an accumulative error;
a subtraction unit to subtract a fixed value from a current code value of the fine code, the subtraction unit to generate a first value;
a first adder to add the first value to the accumulative error from the register, and to store the output as a new accumulative error in the register;
a comparator to compare the new accumulative error with a threshold value; and
a second adder to increment bits of the compensation signal in response to the output of the comparator.
8. The apparatus of claim 7 , wherein the fixed value represents the middle of a range of the fine code.
9. The apparatus of claim 7 , wherein the threshold value is programmable.
10. The apparatus of claim 1 , wherein the logic unit comprises:
a comparator to compare the fine code with a threshold value, the comparator to output a compare signal; and
a filter, coupled to the comparator, to filter the compare signal and to generate the compensation signal.
11. The apparatus of claim 1 , wherein the logic unit is part of the digital filter of the DPLL.
12. The apparatus of claim 1 , wherein the logic unit comprises:
logic for determining a difference between an average fine code and a middle of a range of the fine code;
logic for comparing the difference with a predetermined threshold; and
logic for incrementing or decrementing bits of the compensation signal in response to the comparing.
13. A method comprising:
generating a fine code for controlling a frequency of an output signal of a digitally controlled oscillator (DCO) of a digital phase locked loop (DPLL), the DCO being supplied a power supply level;
monitoring the fine code;
generating a compensation signal based on the monitored fine code; and
updating the power supply level based on the compensation signal.
14. The method of claim 13 , wherein the compensation signal is a temperature compensation signal, and wherein updating the power supply level causes the fine code to be near the middle of an entire range of the fine code across various temperatures.
15. The method of claim 13 , wherein generating the compensation signal comprises:
storing in a register an accumulative error;
subtracting a predetermined value from a current code value, of the fine code, to generate a first value;
adding the first value to the accumulative error from the register;
storing the output as a new accumulative error in the register;
comparing the new accumulative error with a threshold value; and
incrementing or decrementing bits of the compensation signal in response to the comparing.
16. The method of claim 15 , wherein the predetermined value represents the middle of a range of the fine code.
17. The method of claim 13 , wherein generating the compensation signal comprises:
comparing the fine code with a threshold value to generate a compare signal; and
filtering the compare signal to generate the compensation signal.
18. The method of claim 13 , wherein updating the power supply level based on the compensation signal comprises:
generating a reference voltage according to the compensation signal, wherein the updated power supply level is based on the reference voltage.
19. The method of claim 13 , wherein updating the power supply level comprises adjusting an output voltage level of a bandgap reference generator according to the compensation signal.
20. The method of claim 13 , wherein updating the power supply level comprises selecting voltage node from a resistor divider network according to the compensation signal.
21. The method of claim 13 , wherein generating the compensation signal comprises:
determining a difference between an average fine code and a middle of a range of the fine code;
comparing the difference with a predetermined threshold; and
incrementing or decrementing bits of the compensation signal in response to the comparing.
22. A system comprising:
a display; and
a processor coupled to the display, the processor comprising:
a digital phase locked loop (DPLL) including a digital filter to generate a fine code for controlling a frequency of an output signal of a digitally controlled oscillator (DCO) of the DPLL, the DCO being supplied a power supply level;
a logic unit to monitor the fine code and to generate a compensation signal based on the fine code; and
a voltage adjustment unit to update the power supply level based on the compensation signal.
23. The system of claim 22 , wherein the display is a touch pad.
24. The system of claim 22 , wherein the updated power supply level to cause the digital filter to output the fine code to be near the middle of an entire range of the fine code across various temperatures.
25. The system of claim 22 , wherein the voltage adjustment unit comprises:
an adjustable reference voltage generator to generate a reference voltage according to the compensation signal; and
a voltage regulator to generate the updated power supply level for the DCO, the updated power supply level based on the reference voltage.
26. The system of claim 22 , wherein the logic unit comprises:
a register to store an accumulative error;
a subtraction unit to subtract a fixed value from a current code value of the fine code, the subtraction unit to generate a first value;
a first adder to add the first value to the accumulative error from the register, and to store the output as a new accumulative error in the register;
a comparator to compare the new accumulative error with a threshold value; and
a second adder to increment bits of the compensation signal in response to the output of the comparator.
27. The system of claim 22 , wherein the logic unit comprises:
a comparator to compare the fine code with a threshold value, the comparator to output a compare signal; and
a filter coupled to the comparator to filter the compare signal, and to generate the compensation signal.
28. The system of claim 22 , wherein the logic unit comprises:
logic for determining a difference between an average fine code and a middle of a range of the fine code;
logic for comparing the difference with a predetermined threshold; and
logic for incrementing or decrementing bits of the compensation signal in response to the comparing.