IP Library › Granted Patent US 12,493,409
Granted Patent B2
US 12,493,409 · App. 18/502,260 · Granted Dec 9, 2025

Storage system configured to collaborate with host device to implement dynamically adaptive input-output timeout values

Inventors: Sanjib Mallick (Bangalore, IN); Vinay G. Rao (Bangalore, IN); Krishna Deepak Nuthakki (Bangalore, IN); Arieh Don (Newton, MA)
Assignee: Dell Products L.P.
G06F3/0604G06F3/0611G06F3/0659G06F3/0689
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,493,409
App. No.
18/502,260
Filed
Nov 6, 2023
Granted
Dec 9, 2025
Kind
B2
Art Unit
2132
USPC
711/154
Abstract

An apparatus in an illustrative embodiment comprises at least one processing device comprising a processor coupled to a memory. The at least one processing device is configured to receive in a storage system from at least one host device at least first and second different input-output timeout values for respective first and second different logical storage devices of the storage system, to store the received input-output timeout values in association with respective identifiers of the first and second logical storage devices in at least one data structure of the storage system, and to control processing of input-output operations, received in the storage system from the at least one host device and targeting respective ones of the first and second logical storage devices, based at least in part on the corresponding input-output timeout values stored in the at least one data structure of the storage system.

Claims (34)

1 . An apparatus comprising:

at least one processing device comprising a processor coupled to a memory;

the at least one processing device being configured:

to receive in a storage system from at least one host device at least first and second different input-output timeout values for respective first and second different logical storage devices of the storage system;

to store the received input-output timeout values in association with respective identifiers of the first and second logical storage devices in at least one data structure of the storage system; and

to control processing of input-output operations, received in the storage system from the at least one host device and targeting respective ones of the first and second logical storage devices, based at least in part on the corresponding input-output timeout values stored in the at least one data structure of the storage system;

wherein the first and second input-output timeout values comprise respective first and second host-side input-output timeout values, and wherein controlling processing of the input-output operations based at least in part on the corresponding input-output timeout values comprises establishing in the storage system respective first and second storage-side instances of the first and second host-side input-output timeout values for use in the storage system.

2 . The apparatus of claim 1 wherein the at least one processing device comprises at least a portion of the storage system.

3 . The apparatus of claim 1 wherein the first and second logical storage devices have respective first and second different device types.

4 . The apparatus of claim 3 wherein the first and second input-output timeout values are established for the respective first and second logical storage devices based at least in part on their respective first and second device types.

5 . The apparatus of claim 3 wherein the first device type of the first logical storage device comprises a locally-stored device type and the second device type of the second logical storage device comprises a remotely-stored device type and further wherein the first input-output timeout value of the first logical storage device is less than the second input-output timeout value of the second logical storage device.

6 . The apparatus of claim 3 wherein the first device type of the first logical storage device comprises a non-replicated device type and the second device type of the second logical storage device comprises a replicated device type and further wherein the first input-output timeout value of the first logical storage device is less than the second input-output timeout value of the second logical storage device.

7 . The apparatus of claim 1 wherein the first and second storage-side instances of the respective first and second host-side input-output timeout values are less than the respective first and second host-side input-output timeout values.

8 . The apparatus of claim 1 wherein the storage system utilizes the first and second storage-side instances of the first and second host-side input-output timeout values to determine storage-side timeouts for respective ones of the input-output operations received in the storage system from the at least one host device and targeting respective ones of the first and second logical storage devices.

9 . The apparatus of claim 1 wherein the first and second storage-side instances of the respective first and second host-side input-output timeout values are established in the storage system in a manner that ensures that a given one of the input-output operations received in the storage system from a given host device and targeting one of the first and second logical storage devices will time out in the storage system before the given input-output operation times out in the given host device.

10 . The apparatus of claim 1 wherein the storage system receives the first and second different input-output timeout values from the at least one host device in at least one command sent from the at least one host device to the storage system.

11 . The apparatus of claim 1 wherein controlling processing of the input-output operations based at least in part on the corresponding input-output timeout values comprises prioritizing input-output operations targeting one of the first and second logical storage devices having a relatively lower timeout value over input-output operations targeting another one of the first and second logical storage devices having a relatively higher timeout value.

12 . The apparatus of claim 11 wherein the prioritizing of the input-output operations is based at least in part on a combination of the relative timeout values and respective service level objectives associated with the respective first and second logical storage devices.

13 . The apparatus of claim 1 wherein controlling processing of the input-output operations based at least in part on the corresponding input-output timeout values comprises aborting a given input-output operation in the storage system with a retriable status so as to prevent the given input-output operation from timing out in the at least one host device.

14 . A computer program product comprising a non-transitory processor-readable storage medium having stored therein program code of one or more software programs, wherein the program code, when executed by at least one processing device comprising a processor coupled to a memory, causes the at least one processing device:

to receive in a storage system from at least one host device at least first and second different input-output timeout values for respective first and second different logical storage devices of the storage system;

to store the received input-output timeout values in association with respective identifiers of the first and second logical storage devices in at least one data structure of the storage system; and

to control processing of input-output operations, received in the storage system from the at least one host device and targeting respective ones of the first and second logical storage devices, based at least in part on the corresponding input-output timeout values stored in the at least one data structure of the storage system;

wherein the first and second input-output timeout values comprise respective first and second host-side input-output timeout values, and wherein controlling processing of the input-output operations based at least in part on the corresponding input-output timeout values comprises establishing in the storage system respective first and second storage-side instances of the first and second host-side input-output timeout values for use in the storage system.

15 . The computer program product of claim 14 wherein controlling processing of the input-output operations based at least in part on the corresponding input-output timeout values comprises prioritizing input-output operations targeting one of the first and second logical storage devices having a relatively lower timeout value over input-output operations targeting another one of the first and second logical storage devices having a relatively higher timeout value.

16 . A method comprising:

receiving in a storage system from at least one host device at least first and second different input-output timeout values for respective first and second different logical storage devices of the storage system;

storing the received input-output timeout values in association with respective identifiers of the first and second logical storage devices in at least one data structure of the storage system; and

controlling processing of input-output operations, received in the storage system from the at least one host device and targeting respective ones of the first and second logical storage devices, based at least in part on the corresponding input-output timeout values stored in the at least one data structure of the storage system;

wherein the first and second input-output timeout values comprise respective first and second host-side input-output timeout values, and wherein controlling processing of the input-output operations based at least in part on the corresponding input-output timeout values comprises establishing in the storage system respective first and second storage-side instances of the first and second host-side input-output timeout values for use in the storage system.

17 . The method of claim 16 wherein controlling processing of the input-output operations based at least in part on the corresponding input-output timeout values comprises prioritizing input-output operations targeting one of the first and second logical storage devices having a relatively lower timeout value over input-output operations targeting another one of the first and second logical storage devices having a relatively higher timeout value.

18 . The method of claim 16 wherein the first and second storage-side instances of the respective first and second host-side input-output timeout values are less than the respective first and second host-side input-output timeout values.

19 . The method of claim 16 wherein the storage system utilizes the first and second storage-side instances of the first and second host-side input-output timeout values to determine storage-side timeouts for respective ones of the input-output operations received in the storage system from the at least one host device and targeting respective ones of the first and second logical storage devices.

20 . The method of claim 16 wherein the first and second storage-side instances of the respective first and second host-side input-output timeout values are established in the storage system in a manner that ensures that a given one of the input-output operations received in the storage system from a given host device and targeting one of the first and second logical storage devices will time out in the storage system before the given input-output operation times out in the given host device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2023
From: MALLICK, SANJIB; RAO, VINAY G.; NUTHAKKI, KRISHNA DEEPAK; DON, ARIEH
To: DELL PRODUCTS L.P.
Reel/Frame 065465/0387 →
Continuity (1)
Related Publication 20250147658A1 · May 8, 2025
References Cited (134)
US 6567397B1 · Campana, Jr. et al. · 2003 [cited by applicant]
US 6687746B1 · Shuster et al. · 2004 [cited by applicant]
US 6697875B1 · Wilson · 2004 [cited by applicant]
US 7275103B1 · Thrasher et al. · 2007 [cited by applicant]
US 7454437B1 · Lavallee et al. · 2008 [cited by applicant]
US 7617292B2 · Moore et al. · 2009 [cited by applicant]
US 7668981B1 · Nagineni et al. · 2010 [cited by applicant]
US 7770053B1 · Bappe et al. · 2010 [cited by applicant]
US 7809912B1 · Raizen et al. · 2010 [cited by applicant]
US 7818428B1 · Lavallee et al. · 2010 [cited by applicant]
US 7890664B1 · Tao et al. · 2011 [cited by applicant]
US 7904681B1 · Bappe et al. · 2011 [cited by applicant]
US 7925872B2 · Lai et al. · 2011 [cited by applicant]
US 8250256B2 · Ghosalkar et al. · 2012 [cited by applicant]
US 8285825B1 · Nagaraj et al. · 2012 [cited by applicant]
US 8825919B1 · Lim et al. · 2014 [cited by applicant]
US 8832334B2 · Okita · 2014 [cited by applicant]
US 8874746B1 · Gonzalez · 2014 [cited by applicant]
US 9026694B1 · Davidson et al. · 2015 [cited by applicant]
US 9201803B1 · Derbeko et al. · 2015 [cited by applicant]
US 9400611B1 · Raizen · 2016 [cited by applicant]
US 9430368B1 · Derbeko et al. · 2016 [cited by applicant]
US 9594780B1 · Esposito et al. · 2017 [cited by applicant]
US 9647933B1 · Tawri et al. · 2017 [cited by applicant]
US 9672160B1 · Derbeko et al. · 2017 [cited by applicant]
US 9778852B1 · Marshak et al. · 2017 [cited by applicant]
US 10289325B1 · Bono · 2019 [cited by applicant]
US 10353714B1 · Gokam et al. · 2019 [cited by applicant]
US 10439878B1 · Tah et al. · 2019 [cited by applicant]
US 10474367B1 · Mallick et al. · 2019 [cited by applicant]
US 10476960B1 · Rao et al. · 2019 [cited by applicant]
US 10481805B1 · Sahin · 2019 [cited by examiner]
US 10521369B1 · Mallick et al. · 2019 [cited by applicant]
US 10606496B1 · Mallick et al. · 2020 [cited by applicant]
US 10637917B2 · Mallick et al. · 2020 [cited by applicant]
US 10652206B1 · Pusalkar et al. · 2020 [cited by applicant]
US 10754572B2 · Kumar et al. · 2020 [cited by applicant]
US 10757189B2 · Mallick et al. · 2020 [cited by applicant]
US 10764371B2 · Rao et al. · 2020 [cited by applicant]
US 10789006B1 · Gokam et al. · 2020 [cited by applicant]
US 10817181B2 · Mallick et al. · 2020 [cited by applicant]
US 10838648B2 · Sharma et al. · 2020 [cited by applicant]
US 10880217B2 · Mallick et al. · 2020 [cited by applicant]
US 10884935B1 · Doddaiah · 2021 [cited by applicant]
US 10911402B2 · Pusalkar et al. · 2021 [cited by applicant]
US 10936220B2 · Mallick et al. · 2021 [cited by applicant]
US 10936335B2 · Mallick et al. · 2021 [cited by applicant]
US 10949104B2 · Marappan et al. · 2021 [cited by applicant]
US 10996879B2 · Gokam · 2021 [cited by applicant]
US 11016699B2 · Anchi et al. · 2021 [cited by applicant]
US 11016783B2 · Rao et al. · 2021 [cited by applicant]
US 11044313B2 · Patel et al. · 2021 [cited by applicant]
US 11044347B2 · Kumar et al. · 2021 [cited by applicant]
US 11050660B2 · Rao et al. · 2021 [cited by applicant]
US 11093155B2 · Anchi et al. · 2021 [cited by applicant]
US 11106381B2 · Rao et al. · 2021 [cited by applicant]
US 11126358B2 · Kumar et al. · 2021 [cited by applicant]
US 11126363B2 · Tidke et al. · 2021 [cited by applicant]
US 11157203B2 · Gokam et al. · 2021 [cited by applicant]
US 11366771B2 · Smith et al. · 2022 [cited by applicant]
US 11615340B2 · Mallick et al. · 2023 [cited by applicant]
US 20020023151A1 · Iwatani · 2002 [cited by applicant]
US 20020103923A1 · Cherian et al. · 2002 [cited by applicant]
US 20040010563A1 · Forte et al. · 2004 [cited by applicant]
US 20060026346A1 · Kadoiri et al. · 2006 [cited by applicant]
US 20060277383A1 · Hayden et al. · 2006 [cited by applicant]
US 20070174849A1 · Cheung et al. · 2007 [cited by applicant]
US 20080043973A1 · Lai et al. · 2008 [cited by applicant]
US 20080201458A1 · Salli · 2008 [cited by applicant]
US 20080301332A1 · Butler et al. · 2008 [cited by applicant]
US 20090259749A1 · Barrett et al. · 2009 [cited by applicant]
US 20100313063A1 · Venkataraja et al. · 2010 [cited by applicant]
US 20110197027A1 · Balasubramanian et al. · 2011 [cited by applicant]
US 20110296230A1 · Chen et al. · 2011 [cited by applicant]
US 20120102369A1 · Hiltunen et al. · 2012 [cited by applicant]
US 20120246345A1 · Contreras et al. · 2012 [cited by applicant]
US 20130117766A1 · Bax et al. · 2013 [cited by applicant]
US 20130339551A1 · Flanagan et al. · 2013 [cited by applicant]
US 20140105068A1 · Xu · 2014 [cited by applicant]
US 20150222705A1 · Stephens · 2015 [cited by applicant]
US 20150242134A1 · Takada et al. · 2015 [cited by applicant]
US 20160092136A1 · Balakrishnan et al. · 2016 [cited by applicant]
US 20160117113A1 · Li et al. · 2016 [cited by applicant]
US 20160335003A1 · Ahmed et al. · 2016 [cited by applicant]
US 20170235507A1 · Sinha et al. · 2017 [cited by applicant]
US 20180189635A1 · Olarig et al. · 2018 [cited by applicant]
US 20180253256A1 · Bharadwaj · 2018 [cited by applicant]
US 20180317101A1 · Koue · 2018 [cited by applicant]
US 20190095299A1 · Liu et al. · 2019 [cited by applicant]
US 20190108888A1 · Sarkar et al. · 2019 [cited by applicant]
US 20190334987A1 · Mallick et al. · 2019 [cited by applicant]
US 20200021653A1 · Rao et al. · 2020 [cited by applicant]
US 20200097203A1 · Mallick et al. · 2020 [cited by applicant]
US 20200106698A1 · Rao · 2020 [cited by examiner]
US 20200110552A1 · Kumar et al. · 2020 [cited by applicant]
US 20200112608A1 · Patel et al. · 2020 [cited by applicant]
US 20200192588A1 · Kumar et al. · 2020 [cited by applicant]
US 20200204475A1 · Mallick et al. · 2020 [cited by applicant]
US 20200204495A1 · Mallick et al. · 2020 [cited by applicant]
US 20200213274A1 · Pusalkar et al. · 2020 [cited by applicant]
US 20200241890A1 · Mallick et al. · 2020 [cited by applicant]
US 20200314218A1 · Kumar et al. · 2020 [cited by applicant]
US 20200348860A1 · Mallick et al. · 2020 [cited by applicant]
US 20200348861A1 · Marappan et al. · 2020 [cited by applicant]
US 20200348869A1 · Gokam · 2020 [cited by applicant]
US 20200349094A1 · Smith et al. · 2020 [cited by applicant]
US 20200363985A1 · Gokam et al. · 2020 [cited by applicant]
US 20200372401A1 · Mallick et al. · 2020 [cited by applicant]
US 20210019054A1 · Anchi et al. · 2021 [cited by applicant]
US 20210026551A1 · Tidke et al. · 2021 [cited by applicant]
US 20210026650A1 · Rao et al. · 2021 [cited by applicant]
US 20210157502A1 · Rao et al. · 2021 [cited by applicant]
US 20210181965A1 · Anchi et al. · 2021 [cited by applicant]
CN 103677927B · 2017 [cited by applicant]
EP 1117028A2 · 2001 [cited by applicant]
EP 2667569A1 · 2013 [cited by applicant]
International Search Report and Written Opinion of PCT/US2019/052549 dated Dec. 4, 2019, 13 pages. [cited by applicant]
International Search Report and Written Opinion of PCT/US2019/053204 dated Dec. 16, 2019, 40 pages. [cited by applicant]
International Search Report and Written Opinion of PCT/US2019/053473 dated Dec. 19, 2019, 16 pages. [cited by applicant]
International Search Report and Written Opinion of PCT/US2019/067144 dated May 4, 2020, 26 pages. [cited by applicant]
Kris Piepho, “Dell EMC SC Series Storage: Microsoft Multipath I/O,” Dell EMC Best Practices, Jan. 2017, 57 pages. [cited by applicant]
NVM Express, “NVM Express, Revision 1.3,” NVM Express, May 1, 2017, 282 pages. [cited by applicant]
VMWARE, “Multipathing Configuration for Software iSCSI Using Port Binding,” Technical White Paper, Apr. 25, 2012, 15 pages. [cited by applicant]
Dell EMC, “Dell EMC SC Series Storage: Microsoft Multipath I/O,” Dell EMC Engineering, Jun. 2017, 56 pages. [cited by applicant]
Dell EMC, “Dell EMC PowerPath Family: PowerPath and PowerPath/VE Multipathing,” Data Sheet, 2017, 3 pages. [cited by applicant]
EMC, “EMC PowerPath and PowerPath/VE Family for Windows,” Installation and Administration Guide, Oct. 2018, 102 pages. [cited by applicant]
EMC, “EMC Powerpath Load Balancing and Failover”, Comparison with native MPIO operating system solutions, Feb. 2011, 28 pages. [cited by applicant]
Dell EMC, “PowerMax OS,” Dell EMC PowerMax Family Product Guide, May 2019, 192 pages. [cited by applicant]
Dell EMC, “Dell EMC SC Series Storage and Microsoft Multipath I/O,” CML 1004, Jul. 2018, 36 pages. [cited by applicant]
VMWARE, Inc. “VMware VMFS Volume Management,” 2009, 8 pages. [cited by applicant]
Dell EMC, “Dell EMC Unity: Virtualization Integration,” Technical White Paper, Oct. 2019, 39 pages. [cited by applicant]
Dell EMC, “Dell EMC PowerMax: iSCSI Implementation for Dell EMC Storage Arrays Running PowerMaxOS,” Technical White Paper, Sep. 2019, 35 pages. [cited by applicant]
NVM Express, “NVM Express Base Specification, Revision 2.0a,” NVM Express, Jul. 23, 2021, 454 pages. [cited by applicant]
NVM Express, “NVM Express Base Specification, Revision 2.0b,” NVM Express, Jan. 6, 2022, 455 pages. [cited by applicant]