Chip fabrication method and product including raised and recessed alignment structures

1. A method comprising:

etching a first substrate to form a raised alignment structure that extends above a first surface of the first substrate;

etching a second substrate to form a recessed alignment structure that extends below a first surface of the second substrate; and

positioning the raised alignment structure opposite the recessed alignment structure such that the first surface of the first substrate is opposite and parallel to the first surface of the second substrate and such that the raised alignment structure is positioned at least partially within the recessed alignment structure;

wherein the raised alignment structure and recessed alignment structure are shaped such that the raised alignment structure extends at least partially within the recessed alignment structure to a set depth and such that when the raised alignment structure is positioned within the recessed alignment structure at the set depth, movement of the first substrate is restricted towards the second substrate and relative to the second substrate along at least one axis parallel to the first surfaces of the first and second substrates, wherein the method further comprises, before the step of positioning the raised alignment structure opposite the recessed alignment structure, forming quantum circuit components on the first and/or second substrate, wherein forming quantum circuit components comprises:

forming a qubit on the raised alignment structure;

forming a through-substrate via in the second substrate, the through-substrate via extending through the second substrate from the recessed alignment structure to a second surface of the second substrate; and

metallizing the sidewalls of the through-substrate via.

2. The method of claim 1 , wherein:

before positioning the raised alignment structure opposite the recessed alignment structure, the method further comprises depositing at least one of:

a plurality of flip-chip bumps on at least one of the first surface of the first substrate or first surface of the second substrate; or

an indium film on the raised alignment structure and/or within the recessed alignment structure,

positioning the raised alignment structure opposite the recessed alignment structure further comprises bonding the first substrate to the second substrate via the flip-chip bumps or indium film.

3. The method of claim 2 , wherein bonding the first substrate to the second substrate comprises thermocompression bonding, wherein the height of the deposited flip chip bumps is larger than the separation between the first surface of the first substrate and the first surface of the second substrate when the raised alignment structure is positioned within the recessed alignment structure at the set depth and wherein, following compression bonding, the raised alignment structure is positioned within the recessed alignment structure at the set depth.

4. The method of claim 1 , wherein the cross sections of the raised alignment structure and recessed alignment structure along at least one plane perpendicular to the first surfaces of each substrate are trapezium-shaped such that the cross section of the raised alignment structure is a trapezium extending from the first surface of the first substrate and the cross section of the recessed alignment structure is trapezium extending into the first surface of the second substrate.

5. The method of claim 1 , wherein etching a first substrate to form a raised alignment structure comprises forming multiple raised alignment structures on the first substrate and the step of etching a second substrate to form a recessed alignment structure comprises forming multiple recessed alignment structures on the second substrate.

6. The method of claim 5 , wherein the multiple raised alignment structures are arranged on the first substrate and the multiple recessed alignment structures are arranged on the second substrate such that positioning the raised alignment structure opposite the recessed alignment structure comprises positioning each raised alignment structure opposite of the recessed alignment structures such that each raised alignment structure extends at least partially within the opposite recessed alignment structure to the set depth.

7. The method of claim 1 , wherein the method further comprises:

forming multiple raised alignment structures and multiple recessed alignment structures, wherein:

forming a qubit on the raised alignment structure comprises forming qubits on a first subset of the raised alignment structures;

forming a through-substrate via comprises forming through-substrate vias extending from a first subset of the recessed alignment structures, the first subset of recessed alignment structures comprising the recessed alignment structures that are positioned opposite raised alignment structures in the first subset of raised alignment structures in the step of positioning; and

prior to positioning the raised alignment structure opposite the recessed alignment structure, depositing a layer of spacer material on a second subset of the raised alignment structure(s) and/or second subset of the recessed alignment structure(s).

8. The method of claim 7 , wherein the distance between the first substrate and second substrate following positioning the raised alignment structures opposite the recessed alignment structures is determined at least in part by the thickness of the layer of spacer material deposited on the second subset of the raised alignment structure(s) and/or second subset of the recessed alignment structure(s).

9. The method of claim 1 , wherein the method further comprises forming a metallization on at least the side walls of the raised alignment structure surrounding the qubit and wherein positioning the raised alignment structure opposite the recessed alignment structure further comprises placing the metallization on the sidewalls of the through-substrate via in electrical contact with the metallization on the sidewalls of the raised alignment structure.

10. The method of claim 1 , wherein the method further comprises:

forming multiple raised alignment structures and multiple recessed alignment structures, wherein:

forming a qubit on the raised alignment structure comprises forming qubits on at least two of the raised alignment structures and forming a coupler on at least one of the raised alignment structures; and

forming connections elements connecting the at least two qubits to the at least one coupler;

wherein forming a through-substrate via comprises forming through-substrate vias extending from a subset of the recessed alignment structures, the subset of recessed alignment structures comprising the recessed alignment structures that are positioned opposite the raised alignment structures on which the qubits are formed.

11. A product comprising:

a first substrate comprising at least one raised alignment structure that extends above a first surface of the first substrate; and

a second substrate comprising at least one recessed alignment structure that extends below a first surface of the second substrate;

wherein the raised alignment structure is positioned opposite the recessed alignment structure such that the first surface of the first substrate is opposite and parallel to the first surface of the second substrate and such that the raised alignment structure is positioned at least partially within the recessed alignment structure;

wherein the raised alignment structure and recessed alignment structure are shaped such that the raised alignment structure extends at least partially within the recessed alignment structure to a set depth and such that movement of the first substrate is restricted towards the second substrate and relative to the second substrate along at least one axis parallel to the first surfaces of the first and second substrates; and

wherein the product comprises multiple raised alignment structure and multiple recessed alignment structures such that each raised alignment structure extends at least partially within the opposite recessed alignment structure to the set depth, wherein:

the product further comprises a qubit on the raised alignment structure;

a through-substrate via extends from the recessed alignment structure to a second surface of the second substrate; and

the sidewalls of the through-substrate via are metallized.

12. The product of claim 11 , wherein the product further comprises:

a plurality of flip chip bumps connecting the first surface of the first substrate and the first surface of the second substrate; and/or

an indium film on the raised alignment structure and/or within the recessed alignment structure.

13. The product of claim 11 , wherein the cross sections of the raised alignment structure and recessed alignment structure along at least one axis parallel to the first surfaces of each substrate are trapezium-shaped such that the cross section of the raised alignment structure is a trapezium extending from the first surface of the first substrate and the cross section of the recessed alignment structure is a trapezium extending into the first surface of the second substrate.

14. The product of claim 11 , wherein at least one raised alignment structure and at least one recessed alignment structure is present in each quadrant of the substrate.

15. The product of claim 11 , wherein the product comprises multiple raised alignment structures and multiple recessed alignment structures;

a qubit is located on each raised alignment structure in a first subset of the raised alignment structures;

through-substrate vias extend from a first subset of the recessed alignment structures, the first subset of recessed alignment structures comprising the recessed alignment structures that are positioned opposite raised alignment structures in the first subset of raised alignment structures; and

a layer of spacer material is located on a second subset of the raised alignment structure(s) and/or second subset of the recessed alignment structure(s).

16. The product of claim 15 , wherein the distance between the first substrate and second substrate is determined by the thickness of the layer of spacer material located on the second subset of the raised alignment structure(s) and/or second subset of the recessed alignment structure(s).

17. The product of claim 11 , wherein the product further comprises metallization on at least the side walls of the raised alignment structure surrounding the qubit and wherein the metallization on the sidewalls of the through-substrate via is in electrical contact with the metallization on the sidewalls of the raised alignment structure.

18. The product of claim 11 , wherein:

a qubit is located on at least two of the raised alignment structures and a coupler is located on at least one of the raised alignment structures;

connection elements connect the at least two qubits to the at least one coupler;

through-substrate vias extend from a subset of the recessed alignment structures, the subset of recessed alignment structures comprising the recessed alignment structures that are positioned opposite the raised alignment structures on which the qubits are located.