Granted Patent B2

US 12,481,592 · App. 18/504,468 · Granted Nov 25, 2025

Inventors: Rajan Srivastava (Noida, IN); Sourav Roy (Kolkata, IN)

Assignee: NXP USA, Inc.

G06F12/0875G06F12/0811G06F2212/1021

Abstract

Claims (78)

1 . A method of identifying whether an instruction-fetch is a cache-missed instruction in a system on chip (SoC) architecture, the method comprising:

sending an instruction address of a next instruction by a central processing unit (CPU) core to an at-least-one-layer cache;

searching, by an instruction cache controller, the at-least-one-layer cache for the instruction address;

informing, by the instruction cache controller, the CPU core whether the instruction address is present in the at-least-one-layer cache; and

in response to an occurrence of a cache-fetch instruction:

identifying, by a cache hit-miss trace circuit, whether the fetch instruction is a cache-missed instruction and in response to the fetch instruction being identified as a cache-missed instruction, sending a cache miss report message that includes a fetch instruction address to a first trace circuit;

identifying, by the first trace circuit, whether the fetch instruction is a taken-branch instruction and, in response to identifying that the fetch instruction is a taken-branch instruction:

(i) creating a branch trace response message (BTM) and,

(ii) in response to receiving cache miss report from the cache hit-miss trace circuit:

creating a modified BTM that includes the fetch instruction address; and

sending the modified BTM to a create trace messages circuit wherein the modified BTM indicates an instruction address of the cache miss;

determining, by the cache hit-miss trace circuit, whether the cache-fetch instruction is a non-branch cache-miss instruction; and

in response to the fetch instruction being a non-branch cache-miss instruction, generating the cache miss report message that includes an indication of the non-branch cache-miss instruction.

2 . A method of identifying whether an instruction-fetch is a cache-missed instruction in a system on chip (SoC) architecture, the method comprising:

sending an instruction address of a next instruction by a central processing unit (CPU) core to an at-least-one-layer cache;

searching, by an instruction cache controller, the at-least-one-layer cache for the instruction address;

informing, by the instruction cache controller, the CPU core whether the instruction address is present in the at-least-one-layer cache;

in response to an occurrence of a cache-fetch instruction:

identifying, by a cache hit-miss trace circuit, whether the fetch instruction is a cache-missed instruction and in response to the fetch instruction being identified as a cache-missed instruction, sending a cache miss report message that includes a fetch instruction address to a first trace circuit;

identifying, by the first trace circuit, whether the fetch instruction is a taken-branch instruction and, in response to identifying that the fetch instruction is a taken-branch instruction:

(i) creating a branch trace response message (BTM) and,

(ii) in response to receiving cache miss report from the cache hit-miss trace circuit:

creating a modified BTM that includes the fetch instruction address; and

sending the modified BTM to a create trace messages circuit wherein the modified BTM indicates an instruction address of the cache miss;

waiting, by the first trace circuit, to receive a cache miss report within a threshold time-out prior to sending instruction trace log information to the create trace messages circuit; and

adding the cache-miss address of the fetch instruction to the instruction trace log information in response to receiving the cache miss report from the cache hit-miss trace circuit within the threshold time-out.

3 . A system on chip (SoC) architecture comprising:

a central processing unit (CPU) core coupled to an instruction cache controller controlling at least a one layer cache, wherein in response to receiving an instruction address of a next instruction from the CPU core the instruction cache controller is configured to search the at-least-one-layer cache for the instruction address and inform the CPU core whether the instruction address is present in the at-least-one-layer cache; and

an integrated branch and cache hit-miss trace circuit operably coupled to the CPU core and comprising a first trace circuit and a cache hit-miss trace circuit;

wherein the cache hit-miss trace circuit is configured to:

in response to an occurrence of a cache-fetch instruction, identify whether the fetch instruction is a cache-missed instruction,

in response to the cache-fetch instruction being identified as a cache-missed instruction, send a cache-miss report message that includes a fetch instruction address to the first trace circuit,

determine whether the cache-fetch instruction is a non-branch cache-miss instruction, and

in response to the fetch instruction being a non-branch cache-miss instruction, generate the cache miss report message that includes an indication of the non-branch cache-miss instruction;

wherein the first trace circuit is configured to:

in response to an occurrence of the cache-fetch instruction, identify whether the cache-fetch instruction is a taken-branch instruction; and

in response to identifying that the fetch instruction is a taken-branch instruction create a branch trace message (BTM); and

in response to receiving the cache-miss report message from the cache hit-miss trace circuit, include the fetch instruction address in the BTM thereby creating a modified BTM, and send the modified BTM to a create trace messages circuit, wherein the modified BTM indicates an instruction address of the cache miss.

4 . The SoC architecture of claim 3 wherein the cache miss report comprises a cache-miss flag that indicates a cache-miss of the fetch instruction address.

5 . The SoC architecture of claim 3 wherein the CPU core is arranged to store the modified BTM that indicates an instruction address of the cache miss.

6 . The SoC architecture of claim 3 wherein the instruction cache controller controls a multi-layer cache that comprises at least a layer-1 cache and a layer-2 cache.

7 . An integrated circuit for a system on chip (SoC) architecture, the integrated circuit comprising a central processing unit, CPU, core and an integrated branch and cache hit-miss trace circuit configured according to claim 1 .

8 . A system on chip (SoC) architecture comprising:

a central processing unit (CPU) core coupled to an instruction cache controller controlling at least a one layer cache, wherein in response to receiving an instruction address of a next instruction from the CPU core the instruction cache controller is configured to search the at-least-one-layer cache for the instruction address and inform the CPU core whether the instruction address is present in the at-least-one-layer cache; and

an integrated branch and cache hit-miss trace circuit operably coupled to the CPU core and comprising a first trace circuit and a cache hit-miss trace circuit;

wherein the cache hit-miss trace circuit is configured to:

in response to an occurrence of a cache-fetch instruction, identify whether the fetch instruction is a cache-missed instruction, and

in response to the cache-fetch instruction being identified as a cache-missed instruction, send a cache-miss report message that includes a fetch instruction address to the first trace circuit;

wherein the first trace circuit is configured to:

in response to an occurrence of the cache-fetch instruction, identify whether the cache-fetch instruction is a taken-branch instruction;

in response to identifying that the fetch instruction is a taken-branch instruction create a branch trace message (BTM);

in response to receiving the cache-miss report message from the cache hit-miss trace circuit, include the fetch instruction address in the BTM thereby creating a modified BTM, and send the modified BTM to a create trace messages circuit, wherein the modified BTM indicates an instruction address of the cache miss; and

wait to receive a cache miss report within a threshold time-out prior to sending instruction trace log information to the create trace messages circuit and add the cache-miss address of the fetch instruction to the instruction trace log information in response to receiving the cache miss report from the cache hit-miss trace circuit within the threshold time-out.

9 . A system on chip (SoC) architecture comprising:

a central processing unit (CPU) core coupled to an instruction cache controller controlling at least a one layer cache, wherein in response to receiving an instruction address of a next instruction from the CPU core the instruction cache controller is configured to search the at-least-one-layer cache for the instruction address and inform the CPU core whether the instruction address is present in the at-least-one-layer cache; and

an integrated branch and cache hit-miss trace circuit operably coupled to the CPU core and comprising a first trace circuit and a cache hit-miss trace circuit;

wherein the cache hit-miss trace circuit is configured to:

in response to an occurrence of a cache-fetch instruction, identify whether the fetch instruction is a cache-missed instruction, and

in response to the cache-fetch instruction being identified as a cache-missed instruction, send a cache-miss report message that includes a fetch instruction address to the first trace circuit;

wherein the first trace circuit is configured to:

in response to an occurrence of the cache-fetch instruction, identify whether the cache-fetch instruction is a taken-branch instruction;

in response to identifying that the fetch instruction is a taken-branch instruction create a branch trace message (BTM); and

in response to receiving the cache-miss report message from the cache hit-miss trace circuit, include the fetch instruction address in the BTM thereby creating a modified BTM, and send the modified BTM to a create trace messages circuit, wherein the modified BTM indicates an instruction address of the cache miss;

wherein the CPU core stores the modified BTM that indicates an instruction address of the cache miss such that it is accessible for analysis a device external to the SoC to identify which code was executed during time-critical phases of the instruction-tracing period and which code incurred instruction misses.

10 . A system on chip (SoC) architecture comprising:

a central processing unit (CPU) core coupled to an instruction cache controller controlling at least a one layer cache, wherein in response to receiving an instruction address of a next instruction from the CPU core the instruction cache controller is configured to search the at-least-one-layer cache for the instruction address and inform the CPU core whether the instruction address is present in the at-least-one-layer cache; and

an integrated branch and cache hit-miss trace circuit operably coupled to the CPU core and comprising a first trace circuit and a cache hit-miss trace circuit;

wherein the cache hit-miss trace circuit is configured to:

in response to an occurrence of a cache-fetch instruction, identify whether the fetch instruction is a cache-missed instruction, and

in response to the cache-fetch instruction being identified as a cache-missed instruction, send a cache-miss report message that includes a fetch instruction address to the first trace circuit;

wherein the first trace circuit is configured to:

in response to an occurrence of the cache-fetch instruction, identify whether the cache-fetch instruction is a taken-branch instruction;

in response to identifying that the fetch instruction is a taken-branch instruction create a branch trace message (BTM); and

in response to receiving the cache-miss report message from the cache hit-miss trace circuit, include the fetch instruction address in the BTM thereby creating a modified BTM, and send the modified BTM to a create trace messages circuit, wherein the modified BTM indicates an instruction address of the cache miss;

wherein the integrated branch and cache hit-miss trace circuit is operably coupled to a second trace circuit that comprises debug configuration registers and the create trace messages circuit that is configured to include at least one bit that indicates a cache-miss and enables a debugger to perform cache-miss tracing.

11 . The SoC architecture of claim 10 , wherein the second trace circuit comprises a log compression circuit, operably coupled to the first trace circuit, and configured to suppress instruction trace address(es) for non-branch trace message cache-miss instructions.

12 . The SoC architecture of claim 11 , wherein the log compression circuit is operably coupled to on-chip memory, configured to receive an address of the cache miss from the log compression circuit, and to store the address.

13 . The SoC architecture of claim 11 , wherein the log compression circuit is configured to suppress at least one of: a cache miss address's least significant bits (LSB) and a cache miss address's most significant bits (MSB) to align with a cache-line-size of the on-chip memory.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (25)