IP Library › Granted Patent US 12,210,455
Granted Patent B2
US 12,210,455 · App. 17/921,067 · Granted Jan 28, 2025

Recording a memory value trace for use with a separate cache coherency protocol trace

Inventor: Jordi Mola (Bellevue, WA)
Assignee: Microsoft Technology Licensing, LLC
G06F12/0835G06F11/3636G06F12/0891G06F11/3476
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,210,455
App. No.
17/921,067
Granted
Jan 28, 2025
Kind
B2
Abstract

A computer system that records a replayable execution trace based on recording cache coherency protocol (CCP) messages into a first trace, and on recording memory snapshot(s) into a second trace. Based on determining that tracing of execution of a first execution context is to be enabled, the computer system initiates logging, into the second trace, of one or more memory snapshots of a memory space of the first execution context, and enables a hardware tracing feature of a processor. Enabling the tracing feature causes the processor to log, into the first trace, CCP message(s) generated in response to one or more memory access into the memory space of the first execution context. After enabling the hardware tracing feature of the processor, the computer system also logs or otherwise handles a write into the memory space of the first execution context by a second execution context.

Claims (45)

1. A computer system comprising:

a processor comprising a plurality of processing units and a cache;

a memory; and

a computer-readable medium having stored thereon computer-executable instructions that are executable by the processor to cause the computer system to record a replayable execution trace based on recording cache coherency protocol (CCP) messages into a first trace, and on recording one or more memory snapshots into a second trace, the CCP messages being usable to obtain memory values from one or more memory snapshots,

the computer-executable instructions including instructions that are executable by the processor to cause the computer system to at least:

determine that tracing of execution, by the plurality processing units, of a first execution context is to be enabled;

based on determining that tracing of execution of the first execution context is to be enabled:

initiate logging, into the second trace, of one or more memory snapshots of a memory space of the first execution context; and

enable a hardware tracing feature of the processor, which causes the processor to log, into the first trace, one or more CCP messages generated in response to one or more memory access, by one or more of the plurality of processing units, into the memory space of the first execution context;

after enabling the hardware tracing feature of the processor, perform at least one of the following in connection with execution of a second execution context:

log, into one or more of the first trace or the second trace, a write by the second execution context into the memory space of the first execution context;

log, into the second trace, an identity of a file mapped by the second execution context into the memory space of the first execution context;

based at least on the second execution context writing to a cache line in the cache that overlaps with a memory location in memory space of the first execution context, evict, or mark as invalid, the cache line from the cache; or

based at least on the second execution context writing to a memory region within the memory space of the first execution context, mark the memory region as needing to be logged in connection with execution of the first execution context; and encrypt at least a portion of the second trace.

2. The computer system of claim 1 , the computer-executable instructions also including instructions that are executable by the processor to cause the computer system to encrypt the second trace.

3. The computer system of claim 1 , wherein enabling the hardware tracing feature of the processor also causes the processor to flush, from the cache, at least one cache line that overlaps with a memory space of the first execution context.

4. The computer system of claim 1 , wherein the first trace and the second trace are combinable to replay execution of the first execution context.

5. The computer system of claim 4 , wherein the first trace and the second trace are combinable to replay execution of the first execution context based on using the one or more CCP messages logged into the first trace to identify a memory value logged into the one or more memory snapshots within the second trace and that was consumed by at least one of the plurality processing units.

6. The computer system of claim 4 , wherein the first trace and the second trace are combinable to replay execution of the first execution context based on using the one or more CCP messages logged into the first trace to identify a memory value that was consumed by a first of the plurality processing units which was previously written by a second of the plurality processing units.

7. The computer system of claim 1 , wherein initiating logging of the one or more memory snapshots comprises initiating logging of a partial memory snapshot.

8. The computer system of claim 7 , wherein the partial memory snapshot excludes a least one of (i) a paged-out memory page within the memory space of the first execution context, or (ii) a memory page within the memory space of the first execution context that is not accessed by the first execution context.

9. The computer system of claim 1 , wherein initiating logging of the one or more memory snapshots comprises initiating tracking of one or more memory regions within the memory space of the first execution context that are accessed by at least one of the plurality of processing units.

10. The computer system of claim 1 , wherein the computer system logs the write by the second execution context into the memory space of the first execution context.

11. The computer system of claim 10 , wherein logging the write by the second execution context comprises logging a result of a direct memory access (DMA) operation into the second trace.

12. The computer system of claim 1 , wherein the computer system logs the identity of the file mapped by the second execution context into the memory space of the first execution context.

13. The computer system of claim 1 , wherein the computer system evicts the cache line that overlaps with the memory location in memory space of the first execution context, and that is written to by the second execution context.

14. The computer system of claim 1 , wherein, based at least on the second execution context having written to the memory region within the memory space of the first execution context, the computer system marks the memory region as needing to be logged in connection with execution of the first execution context.

15. The computer system of claim 14 , wherein, in connection with a subsequent execution of the first execution context, the computer system logs, into the second trace, at least a portion of the memory region.

16. A method, implemented at a computer system that includes (1) a processor comprising a plurality of processing units and a cache, and (2) a memory, for recording a replayable execution trace based on recording cache coherency protocol (CCP) messages into a first trace, and on recording one or more memory snapshots into a second trace, the CCP messages being usable to obtain memory values from one or more memory snapshots, the method comprising:

determining that tracing of execution, by the plurality processing units, of a first execution context is to be enabled;

based on determining that tracing of execution of the first execution context is to be enabled:

initiating logging, into the second trace, of one or more memory snapshots of a memory space of the first execution context; and

enabling a hardware tracing feature of the processor, which causes the processor to log, into the first trace, one or more CCP messages generated in response to one or more memory access, by one or more of the plurality of processing units, into the memory space of the first execution context; after enabling the hardware tracing feature of the processor, performing at least one of the following in connection with execution of a second execution context:

logging, into one or more of the first trace or the second trace, a write by the second execution context into the memory space of the first execution context;

logging, into the second trace, an identity of a file mapped by the second execution context into the memory space of the first execution context;

based at least on the second execution context writing to a cache line in the cache that overlaps with a memory location in memory space of the first execution context, evicting, or marking as invalid, the cache line from the cache; or

based at least on the second execution context writing to a memory region within the memory space of the first execution context, marking the memory region as needing to be logged in connection with execution of the first execution context; and

encrypting at least a portion of the second trace.

17. The method of claim 16 , wherein the method comprises logging the write by the second execution context into the memory space of the first execution context.

18. The method of claim 16 , wherein the method comprises logging the identity of the file mapped by the second execution context into the memory space of the first execution context.

19. The method of claim 16 , wherein the method comprises evicting the cache line that overlaps with the memory location in memory space of the first execution context, and that is written to by the second execution context.

20. The method of claim 16 , wherein the method comprises marking the memory region as needing to be logged in connection with execution of the first execution context.

21. The computer system of claim 1 , wherein encrypting at least a portion of the second trace includes at least one of:

encrypting at least a portion of the second trace during creation of the second trace; or

encrypting at least a portion of the second trace after creation of the second trace.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2022
From: MOLA, JORDI
To: MICROSOFT TECHNOLOGY LICENSING, LLC
Reel/Frame 061519/0952 →
Priority Claims (1)
LU 101767 · May 5, 2020 · national
Continuity (1)
Related Publication 20230350804A1 · Nov 2, 2023
References Cited (61)
US 8051247B1 · Favor · 2011 [cited by examiner]
US 8370576B1 · Favor · 2013 [cited by examiner]
US 8370609B1 · Favor · 2013 [cited by examiner]
US 8487895B1 · Brown · 2013 [cited by examiner]
US 9195593B1 · Radovic · 2015 [cited by applicant]
US 9432298B1 · Smith · 2016 [cited by examiner]
US 9471313B1 · Busaba · 2016 [cited by examiner]
US 9934127B1 · Mola et al. · 2018 [cited by applicant]
US 9973465B1 · Linkous · 2018 [cited by examiner]
US 9996287B2 · Dornemann · 2018 [cited by examiner]
US 10089230B1 · Koker · 2018 [cited by examiner]
US 10635555B2 · Grosser · 2020 [cited by examiner]
US 11405189B1 · Bennison · 2022 [cited by examiner]
US 11474871B1 · Mittal · 2022 [cited by examiner]
US 12079155B2 · Ray · 2024 [cited by examiner]
US 20020073063A1 · Faraj · 2002 [cited by applicant]
US 20140112339A1 · Safranek · 2014 [cited by examiner]
US 20160239431A1 · Li · 2016 [cited by applicant]
US 20180060215A1 · Mola · 2018 [cited by applicant]
US 20180101483A1 · Catthoor · 2018 [cited by applicant]
US 20180113806A1 · Mola · 2018 [cited by applicant]
US 20180113809A1 · Mola · 2018 [cited by applicant]
US 20180165199A1 · Brandt · 2018 [cited by applicant]
US 20190087305A1 · Mola · 2019 [cited by applicant]
US 20190065339A1 · Mola · 2019 [cited by applicant]
US 20190180407A1 · Goossen et al. · 2019 [cited by applicant]
US 20190220403A1 · Mola · 2019 [cited by applicant]
US 20190258556A1 · Mola · 2019 [cited by applicant]
US 20190266090A1 · Mola · 2019 [cited by applicant]
US 20190286549A1 · Mola et al. · 2019 [cited by applicant]
US 20200026639A1 · Mola · 2020 [cited by applicant]
US 20200349051A1 · Mola · 2020 [cited by applicant]
US 20230169010A1 · Mola · 2023 [cited by applicant]
US 20230176971A1 · Mola · 2023 [cited by applicant]
US 20230342282A1 · Mola · 2023 [cited by applicant]
US 20240095187A1 · Mola · 2024 [cited by applicant]
Kaushik et al., “Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems”, IEEE, pp. 2098-2111 (Year: 2021). [cited by examiner]
Basu et al., “Software Assisted Hardware Cache Coherence for Heterogeneous Processors”, ACM, pp. 1-10 (Year: 2016). [cited by examiner]
Lyu et al, “Directed Test Generation for Validation of Cache Coherence Protocols”, IEEE, pp. 163-176 (Year: 2019). [cited by examiner]
Luo et al., “Public Trace-and-Revoke Proxy Re-Encryption for Secure Data Shring in Clouds”, IEEE, pp. 2919-2934 (Year: 2024). [cited by examiner]
Zakharov et al., “ Time-dependent differential privacy for enhanced data protection in synthetic transaction generation”, ACM, pp. 112-117 (Year: 2024). [cited by examiner]
Ciriani et al., “Combining Fragmentation and Encryption to Protect Privacy in Data Storage”, ACM, pp. 1-33 (Year: 2010). [cited by examiner]
Notice of Allowance mailed on Dec. 20, 2023, in U.S. Appl. No. 17/921,053, 13 pages. [cited by applicant]
Feldman, et al., “Igor: A System for Program Debugging via Reversible Execution”, In Proceedings of ACM SIGPLAN and SIGOPS Workshop on Parallel and Distributed Debugging, Nov. 1, 1988, pp. 112-123. [cited by applicant]
“Search Report and Written Opinion Issued in Luxembourg Patent Application No. LU101767”, Mailed Date: Feb. 26, 2021, 13 Pages. [cited by applicant]
“Search Report and Written Opinion Issued in Luxembourg Patent Application No. LU101768”, Mailed Date: Feb. 10, 2021, 11 Pages. [cited by applicant]
“Search Report and Written Opinion Issued in Luxembourg Patent Application No. LU101769”, Mailed Date: Feb. 5, 2021, 12 Pages. [cited by applicant]
“Search Report and Written Opinion Issued in Luxembourg Application No. LU101770”, Mailed Date: Feb. 5, 2021, 12 Pages. [cited by applicant]
“International Search Report & Written Opinion Issued in PCT Application No. PCT/US21/030199”, Malled Date: Aug. 27, 2021, 15 Pages. [cited by applicant]
“International Search Report & Written Opinion Issued in PCT Application No. PCT/US21/030220”, Mailed Date: Aug. 25, 2021, 16 Pages. [cited by applicant]
“International Search Report & Written Opinion Issued in PCT Application No. PCT/US21/030222”, Mailed Date : Oct. 8, 2021, 18 Pages. [cited by applicant]
“Invitation to Pay Additional Fees Issued in PCT Application No. PCT/US21/030222”, Mailed Date: Aug. 12, 2021, 14 Pages. [cited by applicant]
“International Search Report & Written Opinion Issued in PCT Application No. PCT/US21/030552”, Mailed Date: Feb. 24, 2022, 20 Pages. [cited by applicant]
U.S. Appl. No. 17/921,053, filed May 4, 2021. [cited by applicant]
U.S. Appl. No. 17/921,048, filed Apr. 30, 2021. [cited by applicant]
U.S. Appl. No. 17/921,063, filed Apr. 30, 2021. [cited by applicant]
Dunlap, et al., “ReVirt: Enabling intrusion analysis through virtual-machine logging and replay,” ACM SIGOPS Operating Systems Review 36.SI, 2002, pp. 211-224. [cited by applicant]
Lee, at al., “Design of flash-based DBMS: an in-page logging approach,” Proceedings of the 2007 ACM SIGMOD international conference on Management of data, 2007, pp. 55-66. [cited by applicant]
Notice of Allowance mailed on Jun. 26, 2024, in U.S. Appl. No. 17/921,048, 12 pages. [cited by applicant]
Polyn, et al., “Category-specific cortical activity precedes retrieval during memory search” Science, vol. 310, Issue No. 5756, Dec. 23, 2005, pp. 1963-1966. [cited by applicant]
Non-Final Office Action mailed on Jul. 31, 2024, in U.S. Appl. No. 17/921,063, 18 pages. [cited by applicant]