Low resistance liner
A method of processing a substrate includes forming an amorphous silicon (a-Si) layer over the substrate, where the substrate includes a dielectric layer and a conductive layer, and the a-Si liner covers a surface of the dielectric layer and a surface of the conductive layer. The method includes converting the a-Si liner into a silicon-containing layer including a metal; and depositing the metal over the silicon-containing layer using the silicon-containing layer as a seed layer for the depositing, where the metal deposited over the silicon-containing layer and the conductive layer are electrically connected.
1 . A method of processing a substrate, the method comprising:
forming an amorphous silicon (a-Si) liner over the substrate, the substrate comprising a dielectric layer and a conductive layer, the a-Si liner covering a surface of the dielectric layer and a surface of the conductive layer;
converting the a-Si liner into a silicon-containing layer comprising a metal; and
depositing the metal over the silicon-containing layer using the silicon-containing layer as a seed layer for the depositing, wherein the metal deposited over the silicon-containing layer and the conductive layer are electrically connected.
2 . The method of claim 1 , further comprising, after the depositing, patterning the metal by performing a subtractive dry etch process.
3 . The method of claim 1 , wherein the converting comprises:
exposing the a-Si liner to a vapor comprising the metal; and
heating the substrate to a temperature between 200° C. and 350° C. to react the metal with the a-Si liner.
4 . The method of claim 1 , wherein the converting and the depositing are performed as a single process comprising exposing the substrate to a vapor comprising the metal.
5 . The method of claim 4 , wherein the single process is performed at a temperature between 200° C. and 350° C.
6 . The method of claim 1 , wherein the conductive layer comprises aluminum (Al), copper (Cu), cobalt (Co), tungsten (W), ruthenium (Ru), osmium (Os), molybdenum (Mo), niobium (Nb), or nickel (Ni).
7 . The method of claim 1 , wherein the metal comprises ruthenium (Ru).
8 . The method of claim 1 , wherein the silicon-containing layer comprises a metal silicide.
9 . The method of claim 1 , wherein the silicon-containing layer comprises a metal silicide formed over the conductive layer and a metal silicate formed over the dielectric layer.
10 . A method of processing a substrate, the method comprising:
forming an amorphous silicon (a-Si) liner over a surface of the substrate, the surface comprising a conductive line and a dielectric layer, the substrate comprising a pattern of conductive lines formed within the dielectric layer; and
depositing ruthenium (Ru) over the a-Si liner using a vapor deposition process, wherein a portion of the a-Si liner reacts with a portion of the Ru to form RuSi at an initial stage of the vapor deposition process, and wherein the Ru is deposited over the RuSi.
11 . The method of claim 10 , wherein the a-Si liner has a thickness between 1 nm and 5 nm.
12 . The method of claim 10 , wherein the pattern of conductive lines has a pitch size between 5 nm and 20 nm.
13 . The method of claim 10 , wherein the vapor deposition process is performed at a temperature between 200° C. and 350° C.
14 . The method of claim 10 , wherein the vapor deposition process is an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or a plasma-enhanced CVD (PECVD) process.
15 . The method of claim 10 , wherein the a-Si liner is formed by an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or a plasma-enhanced CVD (PECVD) process.
16 . A method of processing a substrate, the method comprising:
forming a recess in a dielectric layer of the substrate;
filling the recess with ruthenium (Ru) using a chemical vapor deposition (CVD) process;
planarizing a surface of the substrate, the surface after the planarizing comprising the dielectric layer and Ru;
forming an amorphous silicon (a-Si) liner over the surface; and
depositing Ru over the a-Si liner using a physical vapor deposition (PVD) process.
17 . The method of claim 16 , further comprising, after depositing Ru, patterning the PVD-deposited Ru to form a portion of a metal interconnect for a device component fabricated over the substrate.
18 . The method of claim 16 , further comprising, after depositing Ru, performing an annealing process to increase the crystallinity of the PVD-deposited Ru.
19 . The method of claim 16 , wherein the PVD process induces a reaction of the a-Si liner to a layer comprising RuSi, and wherein the layer acts as a seed layer for the Ru deposition.
20 . The method of claim 16 , wherein the PVD process is performed at a temperature between 200° C. and 350° C.