IP Library › Granted Patent US 12,364,033
Granted Patent B2
US 12,364,033 · App. 18/515,288 · Granted Jul 15, 2025

Semiconductor device and method of manufacturing semiconductor device

Inventors: Hajime Watakabe (Tokyo, JP); Akihiro Hanada (Tokyo, JP); Marina Mochizuki (Tokyo, JP); Ryo Onodera (Tokyo, JP); Fumiya Kimura (Tokyo, JP); Isao Suzumura (Tokyo, JP)
Assignee: JAPAN DISPLAY INC.
H10F39/18H10F39/014H10F39/8033H10F39/811
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Quick Facts
Patent No.
US 12,364,033
App. No.
18/515,288
Granted
Jul 15, 2025
Kind
B2
Abstract

The present invention provides a technology which realizes a reliable semiconductor device including a photosensor device by preventing pent roofs of edges of a P + layer from being generated and a metal wiring installed over the P + layer from coming down while securing the electrical conductivity of the P + layer. The semiconductor device includes a photosensor including a photodiode formed on a substrate. The photodiode includes: a cathode electrode; a laminated structure that is formed on the cathode electrode and in which an N + layer, an I layer, and a P + layer are laminated in this order; an anode electrode formed on the P + layer; a first insulating film formed so as to cover a portion of the anode electrode and edges of the laminated structure; and a metal wiring connected to the anode electrode. The edges of the laminated structure are formed in forward tapered shapes in a cross-sectional view.

Claims (26)

1. A method of manufacturing a semiconductor device comprising the steps of:

forming a first organic insulating film on a substrate;

selectively forming a cathode electrode on the first organic insulating film;

forming an N + layer so as to cover an upper portion of the first organic insulating film and the cathode electrode;

forming an I layer so as to cover the N + layer;

forming a P + layer so as to cover the I layer;

executing boron ion implantation on the P + layer after the formation of the P + layer;

selectively forming a resist film on the P + layer; and

executing dry etching on the P + layer, the I layer, and the N + layer using the resist film as a mask.

2. The method of manufacturing a semiconductor device according to claim 1 , wherein, in the step of the boron ion implantation, the boron implantation is executed on the P + layer with an acceleration voltage of about 5 keV.

3. The method of manufacturing a semiconductor device according to claim 2 , wherein the film thickness of the P + layer is about 30 nm.

4. The method of manufacturing a semiconductor device according to claim 3 , wherein, in the step of executing dry etching, edges of a laminated structure composed of the P + layer, the I layer, and the N + layer are formed in forward tapered shapes.

5. The method of manufacturing a semiconductor device according to claim 4 , further comprising the steps of:

forming an anode electrode on the P + layer after the step of executing dry etching;

forming a first insulating film so as to cover a portion of the anode electrode and the edges of the laminated structure;

forming a metal wiring in such a way that the metal wiring is connected to the anode electrode and covers a portion of the first insulating film;

forming a second insulating film so as to cover the first insulating film, a portion of the anode electrode, and the metal wiring.

6. The method of manufacturing a semiconductor device according to claim 5 , further comprising the step of forming a second organic insulating film so as to cover the second insulating film.

7. The method of manufacturing a semiconductor device according to claim 6 ,

wherein the cathode electrode is formed of titanium film, and

the anode electrode is formed of transparent electrically conductive film.

8. The method of manufacturing a semiconductor device according to claim 4 , wherein each of the N + layer, the I layer, and the P + layer is formed of a-Si film.

9. The method of manufacturing a semiconductor device according to claim 8 , wherein is about 50 nm, and

the film thickness of the N + layer

the film thickness of the I layer is about 500 nm.

10. The method of manufacturing a semiconductor device according to claim 1 , further comprising a step of forming a thin film transistor on the substrate before the step of forming the first organic insulating film.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 071619/0050 →
Priority Claims (1)
JP 2020-025023 · Feb 18, 2020 · national
Continuity (2)
Division 17167081 · Feb 4, 2021
Related Publication 20240088192A1 · Mar 14, 2024
References Cited (7)
US 20140103347A1 · Ishino · 2014 [cited by applicant]
US 20140158899A1 · Sugiyama et al. · 2014 [cited by applicant]
CN 103219431A · 2013 [cited by applicant]
JP 5235395A · 1993 [cited by applicant]
JP 2008282844A · 2008 [cited by applicant]
JP 201478651A · 2014 [cited by applicant]
Japanese Office Action issued Oct. 17, 2023, in corresponding Japanese Application No. 2020-025023, 8pp. [cited by applicant]