Low power wake up for memory
View Patent ↗Disclosed herein are related to reducing power consumption of a memory device when transitioning from a sleep state to an operational state. In one aspect, the memory device includes a memory cell to store data. In one aspect, the memory device includes an output driver configured to: generate an output signal indicating the stored data, in response to a sleep tracking signal indicating that the memory cell is in the operational state, and generate the output signal having a predetermined voltage irrespective of the stored data, in response to the sleep tracking signal indicating that the memory cell is in the sleep state. In one aspect, the sleep tracking signal is delayed from a sleep control signal causing the memory cell to operate in the sleep state or the operational state.
1. A memory device comprising:
an output driver coupled to a memory cell storing data;
wherein the output driver is configured to generate an output signal having a predetermined voltage irrespective of the stored data, in response to a sleep tracking signal indicating that the memory cell is in a sleep state; and
wherein the sleep tracking signal is delayed from a sleep control signal and configured to causing the memory cell to operate in the sleep state or the operational state.
2. The memory device of claim 1 , wherein the output driver includes:
a NOR circuit including a first input to receive a signal indicative of the data stored by the memory cell and a second input to receive the sleep tracking signal.
3. The memory device of claim 1 , further comprising:
a sleep control circuit configured to generate the sleep control signal causing the memory cell to transition from the sleep state to the operational state at a first time;
wherein the sleep tracking signal indicates that the memory cell has transitioned from the sleep state to the operational state at a second time after the first time.
4. The memory device of claim 3 , wherein the output driver is configured to maintain the output signal at the predetermined voltage, until the sleep tracking signal indicates that the memory cell has transitioned from the sleep state to the operational state at the second time.
5. The memory device of claim 4 , further comprising:
a delay circuit configured to delay the sleep tracking signal; and
a wake-up detection circuit coupled to the delay circuit, wherein the wake up detection circuit is configured to generate a wake up complete signal indicating whether a transition from the sleep state to the operational state by the memory cell is complete, based on the delayed sleep tracking signal.
6. The memory device of claim 5 , wherein the delay circuit includes one or more buffer circuits.
7. The memory device of claim 5 , wherein the output driver includes:
a power switch to provide a supply voltage to one or more circuits in the output driver, according to the sleep control signal.
8. The memory device of claim 7 , further comprising:
a power detection circuit configured to generate a power detection signal indicating whether the supply voltage of the output driver has reached a threshold voltage.
9. The memory device of claim 8 , wherein the wake-up detection circuit is configured to generate the wake up complete signal, further based on the power detection signal indicating that the supply voltage of the output driver has reached the threshold voltage.
10. The memory device of claim 8 , wherein the wake-up detection circuit includes an OR gate including:
a first input to receive the sleep tracking signal; and
a second input to receive the power detection signal.
11. A memory device comprising:
an output driver coupled to a memory cell storing data, wherein the output driver is configured to generate an output signal having a predetermined voltage irrespective of the stored data, in response to a sleep tracking signal indicating that the memory cell is in a sleep state; and
a sleep control circuit configured to generate a sleep control signal causing the memory cell to transition from the sleep state to an operational state at a first time;
wherein the sleep tracking signal is delayed from the sleep control signal and configured to causing the memory cell to operate in the sleep state or the operational state.
12. The memory device of claim 11 , wherein the sleep tracking signal indicates that the memory cell has transitioned from the sleep state to the operational state at a second time after the first time.
13. The memory device of claim 12 , wherein the output driver is configured to maintain the output signal at the predetermined voltage, until the sleep tracking signal indicates that the memory cell has transitioned from the sleep state to the operational state at the second time.
14. The memory device of claim 13 , further comprising:
a delay circuit configured to delay the sleep tracking signal; and
a wake-up detection circuit coupled to the delay circuit, wherein the wake up detection circuit is configured to generate a wake up complete signal indicating whether a transition from the sleep state to the operational state by the memory cell is complete, based on the delayed sleep tracking signal.
15. The memory device of claim 14 , wherein the delay circuit includes one or more buffer circuits.
16. The memory device of claim 14 , wherein the output driver includes:
a power switch to provide a supply voltage to one or more circuits in the output driver, according to the sleep control signal.
17. The memory device of claim 16 , wherein the wake-up detection circuit is configured to generate the wake up complete signal, further based on the power detection signal indicating that the supply voltage of the output driver has reached the threshold voltage.
18. The memory device of claim 16 , wherein the wake-up detection circuit includes an OR gate including:
a first input to receive the sleep tracking signal; and
a second input to receive the power detection signal.
19. A method comprising:
maintaining an output signal of an output driver coupled to a memory cell that stores data to have a predetermined voltage irrespective of the data stored by the memory cell, until the memory cell has transitioned from a sleep state to an operational state; and
generating the output signal indicating the data stored by the memory cell after the memory cell has transitioned from the sleep state to the operational state.
20. The method of claim 19 , further comprising:
generating a sleep tracking signal indicating whether the memory cell is in the sleep state or in the operational state;
delaying the sleep tracking signal;
generating a wake-up complete signal indicating whether a transition from the sleep state to the operational state by the memory cell is complete, based on the delayed sleep tracking signal; and
generating a power detection signal indicating whether a supply voltage of the output driver has reached a threshold voltage.