System and method of power management in memory design

1. A device comprising:

a first virtual power line, in a first memory bank, configured to be coupled to a power supply through a first group of transistor switches;

a second virtual power line, in a second memory bank, configured to receive the power supply through a second group of transistor switches;

a first delay circuit of the first memory bank having a first input coupled to gate terminals of the first group of transistor switches;

a first delay circuit of the second memory bank having a first input coupled to a first output of the first delay circuit of the first memory bank, the first output of the first delay circuit of the first memory bank coupled to gate terminals in the second group of transistor switches;

a second delay circuit of the second memory bank having a first input coupled to the gate terminals in the second group of transistor switches; and

a first wakeup detector configured to generate a first trigger signal after receiving a signal from a first output of the second delay circuit of the second memory bank.

2. The device of claim 1 , wherein:

the first memory bank includes a first group of bitcells receiving power from the first virtual power line; and

the second memory bank includes a second group of bitcells receiving power from the second virtual power line.

3. The device of claim 1 , wherein the power supply is a power rail.

4. The device of claim 1 , further comprising:

a plurality of main input-output (MIO) controllers configured to be coupled to the power supply through a first group of wakeup switches and through a first group of function switches, wherein gate terminals in the first group of wakeup switches are configured to receive the first trigger signal; and

a first group of local input-output (LIO) controllers configured to be coupled to the power supply through a second group of wakeup switches and through a second group of function switches, and wherein gate terminals of the second group of wakeup switches are configured to receive a delayed signal from the gate terminals of the first group of wakeup switches through one or more stages of delay circuits.

5. The device of claim 4 , further comprising:

a second wakeup detector having an input coupled to the gate terminals in the second group of wakeup switches in the first group of LIO controllers and configured to generate a second trigger signal; and

a plurality of drivers having driver inputs configured to receive the second trigger signal and having driver outputs coupled to gate terminals in the first group of function switches and gate terminals in the second group of function switches.

6. The device of claim 4 , further comprising:

a second group of LIO controllers configured to be coupled to the power supply through a third group of wakeup switches and a third group of function switches; and

a second delay circuit having a second output coupled to the gate terminals in the third group of wakeup switches and having a second input coupled to the gate terminals in the second group of wakeup switches in the first group of LIO controllers.

7. The device of claim 1 , further comprising:

a plurality of MIO controllers configured to be coupled to the power supply through a first group of wakeup switches and through a first group of function switches;

a first group of LIO controllers configured to be coupled to the power supply through a second group of wakeup switches and through a second group of function switches, wherein gate terminals in the second group of wakeup switches are configured to receive the first trigger signal; and

wherein gate terminals of the first group of wakeup switches are configured to receive a delayed signal from gate terminals of second group of wakeup switches through one or more stages of delay circuits.

8. The device of claim 7 , further comprising:

a second wakeup detector coupled to the gate terminals in the first group of wakeup switches and configured to generated a second trigger signal; and

a plurality of drivers having driver inputs configured to receive the second trigger signal and having driver outputs coupled to the gate terminals in the first group of function switches and the gate terminals in the second group of function switches.

9. The device of claim 7 , further comprising:

a second group of LIO controllers configured to be coupled to the power supply through a third group of wakeup switches and a third group of function switches; and

a second delay circuit having a second output coupled to the gate terminals in the third group of wakeup switches and having a second input coupled to the gate terminals in the second group of wakeup switches in the first group of LIO controllers.

10. A device comprising:

a plurality of MIO controllers configured to be coupled to a power supply through a first group of wakeup switches and through a first group of function switches;

a first group of LIO controllers configured to be coupled to the power supply through a second group of wakeup switches and through a second group of function switches;

a wakeup detector configured to generate a trigger signal when voltages levels for powering the plurality of MIO controllers and the first group of LIO controllers reach a predetermine value; and

a plurality of drivers having driver outputs coupled to gate terminals in the first group of function switches and gate terminals in the second group of function switches and having driver inputs configured to receive the trigger signal.

11. The device of claim 10 , wherein the wakeup detector has an input coupled to the gate terminals in the second group of wakeup switches in the first group of LIO controllers.

12. The device of claim 11 , further comprising:

a second group of LIO controllers configured to be coupled to the power supply through a third group of wakeup switches and a third group of function switches; and

a delay circuit having an output coupled to the gate terminals in the second group of wakeup switches in the first group of LIO controllers and having an input coupled to the gate terminals in the third group of wakeup switches in the first group of LIO controllers.

13. The device of claim 10 , wherein the wakeup detector has an input coupled to the gate terminals in the first group of wakeup switches in the MIO controllers.

14. The device of claim 13 , further comprising:

a delay circuit having an output coupled to the gate terminals in the first group of wakeup switches in the MIO controllers and having an input coupled to the gate terminals in the second group of wakeup switches in the first group of LIO controllers.

15. The device of claim 10 , wherein the wakeup detector is a first wakeup detector, the device further comprising:

a second wakeup detector coupled to the gate terminals in the first group of wakeup switches and configured to generate a second trigger signal; and

a plurality of drivers having driver inputs configured to receive the second trigger signal and having driver outputs coupled to the gate terminals in the first group of function switches and the gate terminals in the second group of function switches.

16. A method of activating a memory device that includes a plurality of main input-output (MIO) controllers, a plurality of local input-output (LIO) controllers, a plurality of wakeup switches, a plurality of function switches, and a plurality of memory banks, wherein each memory bank includes a plurality of memory cells, the method comprising:

establishing power connections to the memory cells in a first memory bank, through the wakeup switches associated with the first memory bank;

establishing power connections to the memory cells in a second memory bank, through the wakeup switches associated with the second memory bank, after a predetermined time period after establishing the power connections to the memory cells in the first memory bank; and

providing power connections to the MIO controllers and the LIO controllers, after finishing the power connections to the memory cells in the second memory bank, wherein:

establishing the power connections to a first group of LIO controllers, through the wakeup switches associated with the first group of LIO controllers, at a first time;

establishing the power connections to a second group of LIO controllers, through the wakeup switches associated with the second group of LIO controllers, at a second time; and

establishing the power connections to the MIO controllers, through the wakeup switches associated with the MIO controllers, at a third time.

17. The method of claim 16 , wherein establishing the power connection to a memory cell comprises turning on a transistor switch between a power supply node and a power bus that is conductively connected to the memory cell.

18. The method of claim 16 , wherein providing the power connections to the MIO controller and the LIO controllers further comprises:

establishing further power connections, through the plurality of function switches, to the MIO controllers and to the first group of LIO controllers and the second group of LIO controllers, after finishing the power connections through the wakeup switches to the MIO controllers and to the first group of LIO controllers and the second group of LIO controllers.

19. The method of claim 16 , further comprising:

establishing the power connections to the first group of LIO controllers based on a trigger signal that is generated after finishing the power connections to the memory cells in the second memory bank.

20. The method of claim 16 , further comprising:

establishing the power connections to the MIO controllers based on a trigger signal that is generated at an instant immediately after finishing the power connections to the memory cells in the second memory bank.