IP Library › Granted Patent US 12,432,994
Granted Patent B2
US 12,432,994 · App. 18/520,996 · Granted Sep 30, 2025

Source/drain metal contact and formation thereof

Inventors: Shih-Chuan Chiu (Hsinchu, TW); Tien-Lu Lin (Hsinchu, TW); Yu-Ming Lin (Hsinchu, TW); Chia-Hao Chang (Hsinchu, TW); Chih-Hao Wang (Hsinchu, TW); Jia-Chuan You (Taoyuan County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
H10D62/151H01L21/76871H10D30/024H10D30/62H10D64/017
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Quick Facts
Patent No.
US 12,432,994
App. No.
18/520,996
Granted
Sep 30, 2025
Kind
B2
Abstract

A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.

Claims (48)

1. A contact stack of a semiconductor device, comprising:

a source/drain feature;

a silicide layer wrapping around the source/drain feature;

a seed metal layer in direct contact with the silicide layer; and

a conductor in direct contact with the seed metal layer,

wherein the contact stack excludes a metal nitride layer between the seed metal layer and the silicide layer,

wherein the semiconductor device includes a dielectric liner disposed on a sidewall of the conductor,

wherein the seed metal layer extends on the silicide layer to beyond an outer sidewall of the dielectric liner.

2. The contact stack of claim 1 , wherein the dielectric liner is in direct contact with the conductor and landing on a top surface of the seed metal layer.

3. The contact stack of claim 1 , wherein the semiconductor device further includes a metal gate adjacent to the dielectric liner and an interlayer dielectric (ILD) layer disposed on the outer sidewall of the dielectric liner,

wherein a portion of the seed metal layer is directly below the ILD layer.

4. The contact stack of claim 1 , wherein the seed metal layer wraps around the source/drain feature.

5. The contact stack of claim 1 , wherein the seed metal layer is further disposed below a bottom surface of the source/drain feature.

6. The contact stack of claim 1 , wherein the semiconductor device further includes two fins,

wherein the source/drain feature is disposed over the two fins and has a concave bottom surface, and

wherein the silicide layer includes a portion disposed along the concave bottom surface and sandwiched by the source/drain feature.

7. The contact stack of claim 1 , wherein the silicide layer has a thickness of about 5 nanometers to about 7 nanometers, and

wherein the seed metal layer has a thickness of about 1 nanometer to about 5 nanometers.

8. The contact stack of claim 1 , wherein the semiconductor device further includes a fin and an isolation structure disposed along a sidewall of the fin, and

wherein a portion of the silicide layer is below a topmost surface of the fin in a cross-sectional view including the fin and the isolation structure.

9. A contact stack of a semiconductor device, comprising:

a source/drain feature;

a silicide layer disposed directly on the source/drain feature and extending to a sidewall of the source/drain feature;

a seed metal layer disposed directly on the silicide layer; and

a conductor disposed on the seed metal layer,

wherein the contact stack excludes a metal nitride layer between the seed metal layer and the silicide layer,

wherein the semiconductor device includes a dielectric layer interfacing a first portion of a top surface of the seed metal layer,

wherein the conductor interfaces a second portion of the top surface of the seed metal layer.

10. The contact stack of claim 9 , wherein the silicide layer includes titanium silicide (TiSi), cobalt silicide (CoSi), ruthenium silicide (RuSi), nickel silicide (NiSi), TiSiGe, CoSiGe, RuSiGe, NiSiGe, or a combination thereof.

11. The contact stack of claim 9 , wherein the seed metal layer includes Co, W, Ru, Ni, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, Mo, Zn, K, Cd, Ru, In, Os, Si, or Ge, or combinations thereof.

12. The contact stack of claim 9 , wherein the silicide layer has a thickness of about 5 nanometers to about 7 nanometers, and

wherein the seed metal layer has a thickness of about 1 nanometer to about 5 nanometers.

13. The contact stack of claim 9 , wherein the semiconductor device further includes two fins,

wherein the source/drain feature is a merged source/drain feature disposed over the two fins and having a concave bottom surface, and

wherein the silicide layer includes a third portion disposed below the concave bottom surface and contacting sidewalls of the two fins.

14. The contact stack of claim 13 , wherein the seed metal layer includes a fourth portion disposed below the third portion of the silicide layer and contacting the sidewalls of the two fins.

15. A contact stack of a semiconductor device, comprising:

a source/drain feature;

a silicide layer including a first portion disposed over the source/drain feature and a second portion extending from the first portion and disposed below a bottom surface of the source/drain feature; and

a conductor disposed over the silicide layer.

16. The contact stack of claim 15 , further comprising a seed metal layer disposed over the silicide layer.

17. The contact stack of claim 15 , further comprising a seed metal layer wrapping around the silicide layer,

wherein the seed metal layer includes a portion disposed below the second portion of the silicide layer.

18. The contact stack of claim 15 , wherein the semiconductor device further includes a dielectric layer in direct contact with the contact stack.

19. The contact stack of claim 15 , wherein the semiconductor device further includes a fin structure,

wherein the source/drain feature is disposed over a top surface and sidewalls of the fin structure, and

wherein the silicide layer is in direct contact with the sidewalls of the fin structure.

20. The contact stack of claim 15 , wherein a bottom surface of the second portion of the silicide layer is a concave bottom surface defining a groove.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 28, 2023
From: CHIU, SHIH-CHUAN; LIN, TIEN-LU; LIN, YU-MING; CHANG, CHIA-HAO; WANG, CHIH-HAO; YOU, JIA-CHUAN
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
Reel/Frame 065682/0590 →
Continuity (4)
Continuation 17352682 · Jun 21, 2021
Division 16556922 · Aug 30, 2019
Provisional Application 62753375 · Oct 31, 2018
Related Publication 20240096961A1 · Mar 21, 2024
References Cited (22)
US 6251777B1 · Jeng et al. · 2001 [cited by applicant]
US 8772109B2 · Colinge · 2014 [cited by applicant]
US 8785285B2 · Tsai et al. · 2014 [cited by applicant]
US 8816444B2 · Wann et al. · 2014 [cited by applicant]
US 8823065B2 · Wang et al. · 2014 [cited by applicant]
US 8860148B2 · Hu et al. · 2014 [cited by applicant]
US 9105490B2 · Wang et al. · 2015 [cited by applicant]
US 9236267B2 · De et al. · 2016 [cited by applicant]
US 9236300B2 · Liaw · 2016 [cited by applicant]
US 9472502B1 · Lee et al. · 2016 [cited by applicant]
US 9520482B1 · Chang et al. · 2016 [cited by applicant]
US 9576814B2 · Wu et al. · 2017 [cited by applicant]
US 10566201B1 · Park · 2020 [cited by examiner]
US 10734280B2 · Yim et al. · 2020 [cited by applicant]
US 10832946B1 · Choi et al. · 2020 [cited by applicant]
US 20050239242A1 · Zhu · 2005 [cited by examiner]
US 20160035624A1 · Ogiso · 2016 [cited by applicant]
US 20160315081A1 · Park et al. · 2016 [cited by applicant]
US 20180130707A1 · Clendenning et al. · 2018 [cited by applicant]
US 20190148226A1 · Yim · 2019 [cited by examiner]
US 20200135858A1 · Chiu et al. · 2020 [cited by applicant]
TW 201724273 · 2017 [cited by applicant]