Stacked memory routing techniques
Techniques for signal routing between a host and dynamic random-access memory (DRAM) are provided. In an example, a routing layer for a dynamic random-access memory die (DRAM can include multiple through silicon via (TSV) terminations configured to electrically couple with TSVs of the DRAM, an intermediate interface area, and multiple routing traces. the multiple TSV terminations can be arranged in multiple TSV areas. The multiple TSV areas can be arranged in two columns. The intermediate interface area can include multiple micro-pillar bump terminations configured to couple, via a micro-pillar bump, with corresponding micro-pillar bump terminations of a semiconductor interposer. The multiple routing traces can couple control TSV terminations of the multiple TSV areas with a corresponding micro-pillar bump termination of the intermediate interface.
1 . A memory device, comprising:
a vertical die stack comprising a lowermost die and a memory die interconnected by a plurality of through silicon vias (TSVs); and
a routing layer formed on a lower face of the lowermost die, the routing layer comprising:
respective through silicon via (TSV) terminations electrically coupled with the plurality of TSVs, wherein the respective TSV terminations comprises a first group of TSV terminations and a second group of TSV terminations, and wherein each termination of the first group of TSV terminations is different from each termination of the second group of TSV terminations; and
a plurality of vertically offset routing sublayers comprising:
a first routing sublayer comprising a first set of routing traces, each of the first set of routing traces is used to couple a respective TSV termination of the first group of TSV terminations with corresponding interface termination of an intermediate interface coupled to a host interface or a power supply; and
a second routing sublayer, vertically offset from the first routing sublayer, comprising a second set of routing traces, each of the second set of routing traces is used to couple a respective TSV termination of the second group of TSV terminations with corresponding interface termination of the intermediate interface coupled to the host interface or the power supply.
2 . The memory device of claim 1 , wherein each sublayer of the plurality of vertically offset routing sublayers comprises at least one routing trace.
3 . The memory device of claim 1 , wherein each of the respective TSV terminations is directly coupled with corresponding interface termination using an individual routing trace.
4 . The memory device of claim 3 , wherein the routing layer comprises connections for coupling the intermediate interface to the host interface or the power supply.
5 . The memory device of claim 4 , wherein the connections comprise at least one micro-pillar bump.
6 . The memory device of claim 1 , wherein the memory device is bufferless.
7 . The memory device of claim 1 , wherein the first set of routing traces comprises at least one routing trace having an overshoot path configured to have an equal trace length with another routing trace of the first set of routing traces.
8 . The memory device of claim 7 , wherein a serpentine routing is used for the overshoot path to reduce an overshoot routing area.
9 . The memory device of claim 1 , wherein the first set of routing traces comprises shielded routing traces.
10 . The memory device of claim 1 , wherein the memory die comprises a dynamic random-access memory (DRAM) die.
11 . The memory device of claim 1 , comprising another memory die connected to the memory die via at least one of the plurality of TSVs.
12 . A system comprising:
a memory device comprising:
a vertical die stack comprising a lowermost die and a memory die interconnected by a plurality of through silicon vias (TSVs);
a routing layer formed on a lower face of the lowermost die, the routing layer comprising:
respective through silicon via (TSV) terminations electrically coupled with the plurality of TSVs, wherein the respective TSV terminations comprises a first group of TSV terminations and a second group of TSV terminations, and wherein each termination of the first group of TSV terminations is different from each termination of the second group of TSV terminations;
an intermediate interface comprising a plurality of interface terminations; and
a plurality of vertically offset routing sublayers comprising:
a first routing sublayer comprising a first set of routing traces, each of the first set of routing traces is used to couple a respective TSV termination of the first group of TSV terminations with corresponding interface termination of the plurality of interface terminations; and
a second routing sublayer, vertically offset from the first routing sublayer, comprising a second set of routing traces, each of the second set of routing traces is used to couple a respective TSV termination of the second group of TSV terminations with corresponding interface termination of the plurality of interface terminations;
a host device comprising at least one of a processor, a graphics processing unit, or a system on a chip; and
a semiconductor interposer comprising routing traces connecting the plurality of interface terminations of the intermediate interface to a host interface of the host device.
13 . The system of claim 12 , wherein the memory device is bufferless.
14 . The system of claim 12 , wherein each of the respective TSV terminations is directly coupled with corresponding interface termination of the plurality of interface terminations using an individual routing trace.