Clock monitoring circuit
A clock monitoring circuit includes a clock enable signal generator configured to generate an ultra-high frequency clock enable signal based on a clock enable control signal and a reference clock signal, and an ultra-high frequency detector configured to generate an ultra-high frequency determination signal indicating whether a selection clock signal is an ultra-high frequency signal, based on the selection clock signal, the ultra-high frequency clock enable signal, and the reference clock signal.
1 . A clock monitoring circuit configured to monitor a selection clock signal, the clock monitoring circuit comprising:
a clock enable signal generator configured to generate a high-frequency clock enable signal, a low-frequency clock enable signal, and an ultra-high frequency clock enable signal based on a clock enable control signal and a reference clock signal;
a high-frequency detector configured to generate a high-frequency count value by counting the selection clock signal based on the high-frequency clock enable signal and generate a high-frequency determination signal, which indicates whether the selection clock signal is a high-frequency signal, based on the high-frequency count value;
a low-frequency detector configured to generate a low-frequency count value by counting the selection clock signal based on the low-frequency clock enable signal and generate a low-frequency determination signal based on the low-frequency count value, the low-frequency determination signal indicating whether the selection clock signal is a low-frequency signal;
an ultra-high frequency detector configured to generate an ultra-high frequency determination signal based on the selection clock signal, the ultra-high frequency clock enable signal, and the reference clock signal, the ultra-high frequency determination signal indicating whether the selection clock signal is an ultra-high frequency signal; and
a random frequency detector configured to generate a random frequency determination signal based on the high-frequency clock enable signal and the high-frequency count value, the random frequency determination signal indicating whether frequency shift has occurred to the selection clock signal.
2 . The clock monitoring circuit of claim 1 , wherein the clock enable signal generator is configured to generate the high-frequency clock enable signal, the low-frequency clock enable signal, and the ultra-high frequency clock enable signal by dividing the reference clock signal based on a high-frequency measurement interval, a low-frequency measurement interval, and an ultra-high frequency measurement interval included in the clock enable control signal.
3 . The clock monitoring circuit of claim 2 , wherein the high-frequency measurement interval is shorter than the low-frequency measurement interval.
4 . The clock monitoring circuit of claim 1 , wherein the ultra-high frequency detector comprises:
a resistor-capacitor (RC) filter configured to generate an RC clock signal by filtering the selection clock signal; and
an ultra-high frequency counter configured to generate the ultra-high frequency determination signal based on an ultra-high frequency count value, the ultra-high frequency count value being generated by counting the reference clock signal based on the ultra-high frequency clock enable signal and the RC clock signal.
5 . The clock monitoring circuit of claim 1 , wherein the random frequency detector comprises:
a register circuit configured to shift and store the high-frequency count value based on the high-frequency clock enable signal; and
a random frequency determination circuit configured to generate the random frequency determination signal by comparing a first high-frequency count value stored in the register circuit and a second high-frequency count value stored in the register circuit.
6 . The clock monitoring circuit of claim 1 , further comprising an abnormal frequency determination circuit configured to generate an abnormal frequency determination signal based on the high-frequency determination signal, the low-frequency determination signal, the ultra-high frequency determination signal, and the random frequency determination signal, the abnormal frequency determination signal indicating whether the selection clock signal is defective.
7 . The clock monitoring circuit of claim 6 , wherein the abnormal frequency determination circuit is configured to generate the abnormal frequency determination signal to indicate that the selection clock signal is defective, based on at least one of the high-frequency determination signal, the low-frequency determination signal, the ultra-high frequency determination signal, and the random frequency determination signal indicating that the selection clock signal exhibits an abnormal frequency.