Phase-locked loop, method of operating the same, and devices having the same
A method of operating a phase-locked loop (PLL) such as an all-digital PLL includes operations of comparing a reference clock signal with a feedback signal of the PLL and outputting a comparison signal according to a result of the comparison, and detecting whether the PLL is in a lock state by using a number of times the comparison signal is toggled.
1. A method operating a phase-locked loop (PLL), the method comprising:
comparing a reference clock signal with a feedback signal of the PLL, and outputting a comparison signal according to a result of the comparison; and
detecting whether the PLL is in a lock state according to a number of times the comparison signal is toggled,
wherein the detecting comprises comparing the number of times the comparison signal is toggled with a reference number of times, and detecting whether the PLL is in the lock state, according to the result of the comparison.
2. The method of claim 1 , wherein the detecting further comprises determining the number of times the comparison signal is toggled by counting a number of rising edges or falling edges of the comparison signal.
3. The method of claim 2 , wherein the number of rising edges or falling edges of the comparison signal is counted after an auto frequency control mode is ended.
4. The method of claim 2 , further comprising outputting a lock signal according to a result of the detecting whether the PLL is in the lock state.
5. The method of claim 4 , wherein the determining the number of times the PLL is toggled comprises counting the number of rising edges or falling edges of the comparison signal based on the lock signal when the PLL is in an un-lock state.
6. The method of claim 4 , further comprising controlling a closed-loop bandwidth of the PLL based on the lock signal.
7. The method of claim 1 further comprising:
monitoring whether a mode conversion is needed, based on a control code for controlling a digitally control oscillator included in the PLL in a normal mode; and
converting the normal mode into an automatic frequency control (AFC) mode according to a result of the monitoring.
8. The method of claim 7 , wherein the control code is a code for controlling a total capacitance of a capacitor array associated with the closed-loop bandwidth of the PLL.
9. The method of claim 8 , wherein the monitoring comprises monitoring whether all of the capacitors included in the capacitor array are turned on or off, based on the control code.
10. The method of claim 8 , wherein the monitoring comprises:
determining a capacitor utilization rate associated with the total capacitance, based on the control code; and
comparing the determined capacitor utilization rate with each of a plurality of reference values, and monitoring whether the mode conversion is needed, according to a result of the comparison.
11. The method of claim 10 , wherein the reference values comprise an upper limit reference value and a lower limit reference value.
12. The method of claim 11 , wherein the converting the normal mode into the AFC mode comprises converting the normal mode into the AFC mode when the capacitor utilization rate is greater than the upper limit reference value or is smaller than the lower limit reference value.
13. The method of claim 7 , further comprising:
outputting a monitoring result signal according to a result of the monitoring; and
synchronizing the monitoring result signal with a feedback signal of the PLL,
wherein the converting the normal mode into the AFC mode comprises converting the normal mode into the AFC mode based on a synchronized monitoring result signal corresponding to a result of the synchronizing.
14. A phase-locked loop (PLL) comprising:
a bangbang phase-frequency detector configured to compare a reference clock signal with a feedback signal of the PLL and output a comparison signal according to a result of the comparison; and
a lock detector configured to detect whether the PLL is locked according to a number of times the comparison signal is toggled,
wherein the lock detector is configured to detect whether the PLL is locked by comparing the number of times the comparison signal is toggled with a reference number of times.
15. The PLL of claim 14 , wherein the lock detector comprises:
a counter circuit configured to determine the number of times the comparison signal is toggled; and
a detection circuit configured to detect whether the PLL is locked according to the number of times the comparison signal is toggled.
16. The PLL of claim 15 , wherein the number of times the comparison signal is toggled is a number of rising edges or falling edges of the comparison signal.
17. A system on chip (SoC) comprises:
the PLL of claim 14 ; and
an application processor configured to operate in response to a clock signal associated with an output clock signal of the ADPPL.
18. A portable electronic device comprising:
the SoC of claim 17 ; and
a display that displays data processed by the application processor.