IP Library Granted Patent US 12,445,132
Granted Patent B2
US 12,445,132 · App. 18/525,388 · Granted Oct 14, 2025

Cryptographic hardware sharing systems and methods

Inventors: Tim Vogt (San Jose, CA); Mark Everhard (San Jose, CA); Narasimhakumar Mangipudi (Portland, OR)
Assignee: Lattice Semiconductor Corporation
H03K19/17768H03K19/1737
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Quick Facts
Patent No.
US 12,445,132
App. No.
18/525,388
Granted
Oct 14, 2025
Kind
B2
Abstract

Various techniques are provided to implement cryptographic hardware sharing systems and methods. In one example, a programmable logic device (PLD) includes a configuration engine configured to provide configuration data for processing using a first set of security functions. The PLD further includes a PLD fabric including an array of memory cells configured to operate upon being programmed using the configuration data and provide user data for processing using a second set of security functions. The PLD further includes a security engine including a cryptographic circuit and an interface integration logic circuit. The logic circuit is configured to selectively couple, based on an indicator, the configuration engine or PLD fabric to the cryptographic circuit. The cryptographic circuit is configured to perform the first set or second set of security functions when coupled to the configuration engine or PLD fabric, respectively, by the logic circuit. Related systems and methods are provided.

Claims (49)

1. A programmable logic device (PLD) comprising:

a configuration engine configured to provide configuration data for processing using a first set of security functions;

a PLD fabric comprising an array of memory cells configured to operate upon being programmed based on the configuration data and configured to provide user data for processing using a second set of security functions; and

a security engine comprising:

a cryptographic circuit; and

an interface integration logic circuit configured to selectively couple, based on a security engine control indicator, the configuration engine to the cryptographic circuit or the PLD fabric to the cryptographic circuit, wherein the cryptographic circuit is configured to perform the first set of security functions for the configuration engine when coupled to the configuration engine by the interface integration logic circuit and/or the second set of security functions for the PLD fabric when coupled to the PLD fabric by the interface integration logic circuit.

2. The PLD of claim 1 , wherein the interface integration logic circuit comprises:

a first multiplexer circuit configured to selectively route, based on the security engine control indicator, output data from the cryptographic circuit to the configuration engine or the PLD fabric; and

a second multiplexer circuit configured to selectively route, based on the security engine control indicator, output data from the configuration engine or the PLD fabric to the cryptographic circuit.

3. The PLD of claim 2 , wherein, when the security engine control indicator has a value indicating the configuration engine has control of the security engine, the first multiplexer circuit is configured to receive the output data from the cryptographic circuit on a first data interface connecting the cryptographic circuit to the first multiplexer circuit and route the output data on the first data interface to a second data interface connected to the configuration engine.

4. The PLD of claim 1 , wherein the interface integration logic circuit comprises a clock domain crossing circuit configured to connect to the PLD fabric on one end and the cryptographic circuit on another end.

5. The PLD of claim 1 , wherein the configuration engine is configured to transmit information associated with the first set of security functions to a first mailbox on a control interface connecting the configuration engine to the first mailbox, and wherein the cryptographic circuit is configured to perform the first set of security functions based in part on the information.

6. The PLD of claim 5 , wherein the first mailbox forms a part of the interface integration logic circuit or the cryptographic circuit.

7. The PLD of claim 5 , wherein the PLD fabric is configured to transmit information associated with the second set of security functions to a second mailbox on a control interface connecting the PLD fabric to the second mailbox.

8. The PLD of claim 1 , wherein:

the PLD fabric is configured to transmit a first control request signal to the configuration engine or the security engine;

the security engine is configured to transition the security engine control indicator to a value indicative of control of the security engine by the PLD fabric in response to the first control request signal; and

the interface integration logic circuit is configured to couple the PLD fabric to the cryptographic circuit in response to the transitioned security engine control indicator.

9. The PLD of claim 8 , wherein:

the PLD fabric is configured to transmit the first control request signal to the configuration engine;

the configuration engine is configured to transmit a control transfer request signal to the security engine in response to the first control request signal;

the security engine is configured to, in response to the control transfer request signal, transmit a control transfer response to the configuration engine and transition the security engine control indicator;

the configuration engine is configured to deassert a security engine usage indicator in response to the control transfer response; and

the PLD fabric is configured to determine whether the PLD fabric has control of the security engine based on the security engine usage indicator.

10. The PLD of claim 8 , wherein:

the configuration engine is configured to transmit a second control request signal to the security engine;

the security engine is configured to further transition the security engine control indicator to a value indicative of control of the security engine from the PLD fabric back to the configuration engine in response to the second control request signal; and

the interface integration logic circuit is configured to couple the configuration engine to the cryptographic circuit in response to the further transitioned security engine control indicator.

11. The PLD of claim 1 , wherein the first set of security functions comprises authenticating and/or decrypting the configuration data, and/or wherein the second set of security functions comprises true random number generation, hashing, encryption, authentication, and/or key generation associated with the user data.

12. A method comprising:

selectively coupling, by an interface integration logic circuit based on a security engine control indicator, a configuration engine to a cryptographic circuit or a programmable logic device (PLD) fabric to the cryptographic circuit;

performing a first set of security functions on configuration data from the configuration engine if the cryptographic circuit is coupled to the configuration engine by the interface integration logic circuit, wherein the PLD fabric comprises an array of memory cells programmed based on the configuration data; and

performing a second set of security functions on user data from the PLD fabric if the cryptographic circuit is coupled to the PLD fabric by the interface integration logic circuit.

13. The method of claim 12 , wherein the selectively coupling comprises:

selectively routing, by a first multiplexer circuit based on the security engine control indicator, output data from the cryptographic circuit to the configuration engine or the PLD fabric; and

selectively routing, by a second multiplexer circuit based on the security engine control indicator, output data from the configuration engine or the PLD fabric to the cryptographic circuit.

14. The method of claim 13 , wherein, when the security engine control indicator has a value indicating the configuration engine has control of the security engine, the first multiplexer circuit receives the output data from the cryptographic circuit on a first data interface connecting the cryptographic circuit to the first multiplexer circuit and routes the output data on the first data interface to a second data interface connected to the configuration engine.

15. The method of claim 12 , further comprising transmitting, by the configuration engine, information associated with the first set of security functions to a first mailbox on a control interface connecting the configuration engine to the first mailbox, wherein the performing the first set of security functions is based in part on the information.

16. The method of claim 15 , further comprising transmitting, by the PLD fabric, information associated with the second set of security functions to a second mailbox on a control interface connecting the PLD fabric to the second mailbox.

17. The method of claim 16 , wherein the second mailbox forms a part of the interface integration logic circuit or the cryptographic circuit.

18. The method of claim 12 , further comprising:

transmitting, by the PLD fabric, a control request signal to the configuration engine or the security engine; and

transitioning, by the security engine, the security engine control indicator to a value indicative of control of the security engine by the PLD fabric in response to the control request signal, wherein the interface integration logic circuit couples the PLD fabric to the cryptographic circuit in response to the transitioned security engine control indicator.

19. The method of claim 18 , wherein the PLD fabric transmits the control request signal to the configuration engine, the method further comprising:

transmitting, by the configuration engine, a control transfer request signal to the security engine in response to the control request signal;

transmitting, by the security engine, a control transfer response to the configuration engine;

deasserting, by the configuration engine, a security engine usage indicator in response to the control transfer response; and

determining, by the PLD fabric, whether the PLD fabric has control of the security engine based on the security engine usage indicator.

20. The method of claim 12 , wherein the first set of security functions comprises authenticating and/or decrypting the configuration data, and/or wherein the second set of security functions comprises true random number generation, hashing, encryption, authentication, and/or key generation associated with the user data.

Assignments (2)
SECURITY INTEREST Recorded Jul 2, 2026
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 075892/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 24, 2025
From: VOGT, TIM; EVERHARD, MARK; MANGIPUDI, NARASIMHAKUMAR
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 071823/0334 →
Continuity (2)
Provisional Application 63429777 · Dec 2, 2022
Related Publication 20240187001A1 · Jun 6, 2024
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