Patent Assignment
Reel/Frame 075892/0001
Security Interest
Recorded: 2026-07-02
Pages: 50
Assignor
LATTICE SEMICONDUCTOR CORPORATION
Executed: 2026-06-30
Assignee
WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
P.O. BOX 760776, MAC T7422-012, SAN ANTONIO, TEXAS, 78245
Covered Properties
(459)
Scalable Data Structure for Aggregating Bmc Input and Output Over Serdes for Data Center and Server Nodes System and Method
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19/547,567 →
Publication:
US US20260187001A1
System and Method for Gaze-Driven Computer Control
Application:
19/452,081 →
Publication:
US US20260147409A1
Flexible Bitstream Verification and Integrity Checking for Programable Logic Devices, Systems, and Methods
Application:
19/445,400 →
Publication:
US US20260220309A1
Device Attestation Over Ltpi Interface Using Privileged Mode Systems and Methods
Application:
19/296,884 →
Publication:
US US20260163891A1
Off-Chip Keystore Systems and Methods
Application:
19/007,159 →
Publication:
US US20260189383A1
Physical Coding Sublayer Datapath Systems and Methods with Deterministic Latency
Application:
18/924,915 →
Publication:
US US20250138570A1
Root of Trust Chain and Updatable Security for Programable Logic Devices, Systems, and Methods
Application:
18/916,352 →
Publication:
US US20250131081A1
Image Tagging Engine Systems and Methods for Programmable Logic Devices
Application:
18/820,155 →
Publication:
US US20240420492A1
Efficient Component Mapping for Programable Logic Devices, Systems, and Methods
Application:
18/810,215 →
Publication:
US US20250068818A1
Pipeline Architecture for Configuring Programmable Logic Device Systems and Methods
Application:
18/666,692 →
Publication:
US US20240385848A1
Method and Systems to Align Output Signals of an Analog-to-Digital Converter
Patent:
7,348,914 →
Application:
11/477,759 →
Reconfiguration of Programmable Logic Devices
Patent:
7,375,549 →
Application:
11/350,436 →
Detection of Unknown Symbol Rate in a Digitally Modulated Signal
Patent:
7,376,204 →
Application:
11/083,625 →
Programmable Logic Device Architecture with Multiple Slice Types
Patent:
7,378,872 →
Application:
11/445,620 →
Programmable Logic Device Providing a Serial Peripheral Interface
Patent:
7,378,873 →
Application:
11/446,548 →
Dual Slice Architectures for Programmable Logic Devices
Patent:
7,385,417 →
Application:
11/446,542 →
Logic Block Control Architectures for Programmable Logic Devices
Patent:
7,397,276 →
Application:
11/446,351 →
Video Stream Routing and Format Conversion Unit with Audio Delay
Patent:
7,400,359 →
Application:
10/753,909 →
Single-Ended Output Driver Buffer
Patent:
7,411,414 →
Application:
11/877,434 →
Selective Loading of Configuration Data into Configuration Memory Cells
Patent:
7,411,417 →
Application:
11/442,186 →
Programmable Logic Function Generator Using Non-Volatile Programmable Memory Switches
Low Static Current Drain Logic Circuit
Output Buffer with Digital Slew Control
Patent:
7,443,192 →
Application:
11/643,288 →
Comparator Systems and Methods
Patent:
7,446,573 →
Application:
11/361,643 →
Clock Systems and Methods
Patent:
7,456,672 →
Application:
11/530,620 →
Programmable Logic Device and Method of Testing
Patent:
7,463,060 →
Application:
11/452,714 →
Data Transmission Synchronization
Temperature-Independent, Linear on-Chip Termination Resistance
Digital I/O Timing Control
Flexible Memory Architectures for Programmable Logic Devices
Patent:
7,495,970 →
Application:
11/446,309 →
Receiver for Differential and Reference-Voltage Signaling with Programmable Common Mode
Patent:
7,505,752 →
Application:
11/189,067 →
Clock Boosting Systems and Methods
Patent:
7,509,598 →
Application:
11/737,702 →
Signal Monitoring Systems and Methods
Patent:
7,519,139 →
Application:
11/185,242 →
Switch Sequencing Circuit Systems and Methods
Distributed Multiple-Channel Alignment Scheme
Register Data Retention Systems and Methods During Reprogramming of Programmable Logic Devices
Patent:
7,535,253 →
Application:
11/941,006 →
Logic Analyzer Systems and Methods for Programmable Logic Devices
Patent:
7,536,615 →
Application:
11/691,003 →
Transparent Field Reconfiguration for Programmable Logic Devices
Patent:
7,538,574 →
Application:
11/293,941 →
Programmable Logic Devices with Custom Identification Systems and Methods
Patent:
7,546,498 →
Application:
11/446,308 →
Dynamic Over-Voltage Protection Scheme for Interface Circuitry
Patent:
7,547,995 →
Application:
11/345,713 →
Efficient Configuration of Daisy-Chained Programmable Logic Devices
Programmable Logic Devices with User Non-Volatile Memory
Patent:
7,554,358 →
Application:
11/397,985 →
Synchronization of Data Signals and Clock Signals for Programmable Logic Devices
Patent:
7,557,606 →
Application:
12/105,146 →
Power Management Systems and Methods for Programmable Logic Devices
Patent:
7,560,953 →
Application:
12/107,883 →
Programmable Logic Device Providing Serial Peripheral Interfaces
Patent:
7,570,078 →
Application:
11/761,221 →
Covert Channel for Conveying Supplemental Messages in a Protocol-Defined Link for a System of Storage Devices
Distributed Front-End Fifo for Source-Synchronized Interfaces with Non-Continuous Clocks
Patent:
7,573,770 →
Application:
11/778,457 →
High Fan-Out Signal Routing Systems and Methods
Patent:
7,576,563 →
Application:
11/671,948 →
Integrated Circuit Having Independent Voltage and Process/Temperature Control
Patent:
7,586,325 →
Application:
11/949,130 →
Dynamic Delay or Advance Adjustment of Oscillating Signal Phase
Patent:
7,586,344 →
Application:
11/872,950 →
Current Mode Circuitry to Modulate a Common Mode Voltage
Data Decompression
Patent:
7,589,648 →
Application:
11/054,855 →
Auto Recovery from Volatile Soft Error Upsets (Seus)
Patent:
7,596,744 →
Application:
11/361,584 →
Redundant Configuration Memory Systems and Methods
Clock-And-Data-Recovery System Having a Multi-Phase Clock Generator for One or More Channel Circuits
Adaptive Bandwidth Phase Locked Loop with Feedforward Divider
Low-Power Output Driver Buffer Circuit
Patent:
7,605,602 →
Application:
12/188,120 →
Area Efficient Routing Architectures for Programmable Logic Devices
Patent:
7,605,606 →
Application:
11/498,646 →
Programmable Level Shifter
Patent:
7,605,609 →
Application:
11/957,598 →
Correlator Having User-Defined Processing
Hysteresis-Based Processing for Applications Such as Signal Bias Monitors
Patent:
7,616,029 →
Application:
11/869,019 →
Jitter Tolerant Delay-Locked Loop Circuit
Selective Programming of Non-Volatile Memory Facilitated by Security Fuses
Patent:
7,623,378 →
Application:
11/416,881 →
Data Transfer Verification Systems and Methods
Patent:
7,623,391 →
Application:
11/624,021 →
Programmable Logic Device with Built in Self Test
Patent:
7,630,259 →
Application:
11/959,329 →
Analog-To-Digital Systems and Methods
Patent:
7,630,464 →
Application:
11/109,301 →
Programmable Logic Device Methods and System for Providing Multi-Boot Configuration Data Support
Patent:
7,631,223 →
Application:
11/447,591 →
Integrated Circuit Temperature Sensor Systems and Methods
Patent:
7,632,011 →
Application:
11/750,616 →
Flash Memory Array with Independently Erasable Sectors
Patent:
7,636,259 →
Application:
11/487,647 →
Multi-Port Memory Device Having Variable Port Speeds
Programmable Logic Device and Method of Testing
Patent:
7,656,193 →
Application:
12/327,128 →
Clock Distribution Chip for Generating Both Zero-Delay and Non-Zero-Delay Clock Signals
Patent:
7,657,773 →
Application:
11/425,881 →
On-Chip Temperature Sensor for an Integrated Circuit
Patent:
7,661,878 →
Application:
12/099,933 →
Multiplexer Initialization Systems and Methods
Patent:
7,663,401 →
Application:
11/556,528 →
Clock Systems and Methods
Patent:
7,663,419 →
Application:
12/273,868 →
Methods and Systems for Storing a Security Key Using Programmable Fuses
Patent:
7,675,313 →
Application:
11/498,645 →
Weight Based Look Up Table Collapsing for Programmable Logic Devices
Patent:
7,681,160 →
Application:
11/863,016 →
Fast-Carry Arithmetic Circuit Using a Multi-Input Look-Up Table
Patent:
7,685,215 →
Application:
11/257,137 →
Design Features for Testing Integrated Circuits
Patent:
7,685,483 →
Application:
11/157,345 →
Error Detection in Physical Interfaces for Point-to-Point Communications Between Integrated Circuits
Key Generation for Advanced Encryption Standard (Aes) Decryption and the Like
Time Base Correction and Frame Rate Conversion
Patent:
7,710,501 →
Application:
10/889,855 →
Power Management for Integrated Circuits Such as Programmable Logic Devices
Patent:
7,724,029 →
Application:
12/502,141 →
Programmable Logic Device Programming Verification Systems and Methods
Patent:
7,725,803 →
Application:
11/557,808 →
Serial Interface for Programmable Logic Devices
Patent:
7,728,625 →
Application:
12/001,600 →
Logic Analyzer Systems and Methods for Programmable Logic Devices
Patent:
7,743,296 →
Application:
11/691,040 →
Redundant Configuration Memory Systems and Methods
Patent:
7,746,107 →
Application:
12/564,781 →
Scan Chain Systems and Methods for Programmable Logic Devices
Patent:
7,757,198 →
Application:
11/875,748 →
Dynamic Phase Offset Measurement
Coding System for Memory Systems Employing High-Speed Serial Links
Programmable Logic Device with a Multi-Data Rate Sdram Interface
Patent:
7,787,326 →
Application:
12/019,526 →
Input/Output Placement Systems and Methods to Reduce Simultaneous Switching Output Noise
Patent:
7,788,620 →
Application:
11/937,328 →
Composite Wire Indexing for Programmable Logic Devices
Patent:
7,788,623 →
Application:
11/947,662 →
Efficient Bitstream Compression
Patent:
7,808,405 →
Application:
12/413,787 →
Distributed Front-End Fifo for Source-Synchronous Interfaces with Non-Continuous Clocks
Patent:
7,808,855 →
Application:
12/538,810 →
Multiple Communication Channel Configuration Systems and Methods
Patent:
7,831,754 →
Application:
11/551,459 →
Shared Nonvolatile Memory Architecture
Detection of Timing Errors in Programmable Logic Devices
Patent:
7,831,856 →
Application:
12/061,885 →
Method and Devices for Storing a Security Key Using Programmable Fuses
Patent:
7,834,652 →
Application:
12/709,685 →
Parallel Interface Bus to Communicate Video Data Encoded for Serial Data Links
Power-Saving Clocking Technique
Flexible Delay Cell Architecture
Patent:
7,863,931 →
Application:
11/939,787 →
Reading an External Memory Device to Determine Its Interface Characteristics for Configuring a Programmable Logic Device
Patent:
7,868,654 →
Application:
12/465,444 →
Register Data Retention Systems and Methods During Reprogramming of Programmable Logic Devices
Patent:
7,876,125 →
Application:
12/464,822 →
Wire Mapping for Programmable Logic Devices
Patent:
7,890,913 →
Application:
12/055,170 →
Simultaneous Switching Output Noise Estimation and Reduction Systems and Methods
Patent:
7,895,555 →
Application:
11/937,300 →
Formation of High Voltage Transistor with High Breakdown Voltage
Patent:
7,897,448 →
Application:
12/122,489 →
Compression and Decompression of Configuration Data Using Repeated Data Frames
Patent:
7,902,865 →
Application:
11/941,031 →
Progressive Power Control of a Multi-Port Memory Device
Packet Level Prioritization in Interconnection Networks
Synchronizing Related Data Streams in Interconnection Networks
Digital Video Interface with Bi-Directional Half-Duplex Clock Channel Used as Auxiliary Data Channel
Programmable Logic Device with Built in Self Test
Patent:
7,944,765 →
Application:
12/626,289 →
Inter-Port Communication in a Multi-Port Memory Device
Flexible Memory Architectures for Programmable Logic Devices
Patent:
7,957,208 →
Application:
12/389,149 →
Oscillator Tuning for Phase-Locked Loop Circuit
Patent:
7,969,248 →
Application:
12/512,961 →
17B/20B Coding System
Edge Detection
Concurrent Code Checker and Hardware Efficient High-Speed I/O Having Built-in Self-Test and Debug Features
Congestion Estimation for Programmable Logic Devices
Patent:
7,992,120 →
Application:
12/323,974 →
Bank Sharing and Refresh in a Shared Multi-Port Memory Device
Original Scan Line Detection
Auto Recovery from Volatile Soft Error Upsets (Seus)
Patent:
8,010,871 →
Application:
12/561,140 →
Planar Antenna
Patent:
8,022,887 →
Application:
11/588,472 →
Fault Testing for Interconnections
Separate Configuration of I/O Cells and Logic Core in a Programmable Logic Device
Patent:
8,040,152 →
Application:
12/698,283 →
Comparator with Jitter Mitigation
Patent:
8,040,159 →
Application:
12/729,952 →
Fpga Having Low Power, Fast Carry Chain
Compression and Decompression of Configuration Data Using Repeated Data Frames
Patent:
8,058,898 →
Application:
13/034,174 →
Flash Memory Array with Independently Erasable Sectors
Patent:
8,059,470 →
Application:
12/611,262 →
Programmable Logic Device and Methods for Providing Multi-Boot Configuration Data Support
Patent:
8,060,784 →
Application:
12/630,163 →
Equalizer with Controllably Weighted Parallel High Pass and Low Pass Filters and Receiver Including Such an Equalizer
Patent:
8,064,508 →
Application:
10/247,675 →
Soft Error Detection Logic Testing Systems and Methods
Patent:
8,065,574 →
Application:
11/760,411 →
Internally Triggered Reconfiguration of Programmable Logic Devices
Patent:
8,069,329 →
Application:
12/021,202 →
Routing Signals to Pins of Components in Programmable Logic Devices
Patent:
8,069,431 →
Application:
12/406,772 →
Noise Cancellation
Group Power Management of Network Devices
Clock Boosting Systems and Methods
Patent:
8,086,986 →
Application:
12/408,047 →
Wire Mapping for Programmable Logic Devices
Patent:
8,104,009 →
Application:
13/026,555 →
Programmable Logic Device Programming Verification Systems and Methods
Patent:
8,108,754 →
Application:
12/786,359 →
Clock Distribution Chip
Patent:
8,112,656 →
Application:
12/578,492 →
Congestion-Driven Placement Systems and Methods for Programmable Logic Devices
Patent:
8,112,731 →
Application:
12/277,217 →
Source-Adaptive Video Deinterlacer
Clock Distribution Chip
Patent:
8,122,277 →
Application:
12/578,470 →
Channel-To-Channel Deskew Systems and Methods
Patent:
8,132,040 →
Application:
11/924,088 →
Data Stream Control for Network Devices
Signal Interleaving for Serial Clock and Data Recovery
Shared-Array Multiple-Output Digital-to-Analog Converter
Patent:
8,164,499 →
Application:
12/813,540 →
In-System Reconfigurable Circuit for Mapping Data Words of Different Lengths
Patent:
8,165,164 →
Application:
12/494,822 →
Comparator with Jitter Mitigation
Patent:
8,169,237 →
Application:
13/275,102 →
Multi-Priority Placement for Configuring Programmable Logic Devices
Patent:
8,181,139 →
Application:
12/341,929 →
Method and System for Detecting Successful Authentication of Multiple Ports in a Time-Based Roving Architecture
Ensuring Physical Locality of Entities Sharing Data
Methods and Mechanisms for Probabilistic Color Correction
Low-Power, Glitch-Less, Configurable Delay Element
Patent:
8,248,136 →
Application:
13/007,804 →
Clock Delay and Skew Control Systems and Methods
Patent:
8,255,733 →
Application:
12/512,944 →
Displacement Sensing Using a Flexible Substrate
Synchronization of Serial Data Signals
Patent:
8,261,160 →
Application:
12/182,940 →
Serializer with Odd Gearing Ratio
Patent:
8,274,412 →
Application:
12/987,393 →
Composite Wire Indexing for Programmable Logic Devices
Patent:
8,286,116 →
Application:
12/871,764 →
Method and System for Placing Integrated Circuits into Predominantly Ultra-Low Voltage Mode for Standby Purposes
Patent:
8,314,632 →
Application:
13/193,984 →
Power Control Block with Output Glitch Protection
Patent:
8,314,634 →
Application:
13/079,578 →
Safe Programming of Key Information into Non-Volatile Memory for a Programmable Logic Device
Patent:
8,319,521 →
Application:
13/076,300 →
Programmable Buffer
Patent:
8,324,934 →
Application:
13/007,688 →
De-Encapsulation of Data Streams into Multiple Links
Method, Apparatus and System for Employing a Content Protection System
Bitline Floating Circuit for Memory Power Reduction
Patent:
8,351,287 →
Application:
12/976,412 →
Programmable Logic Device Wakeup Using a General Purpose Input/Output Port
Patent:
8,368,424 →
Application:
13/038,259 →
Testing of Soft Error Detection Logic for Programmable Logic Devices
Patent:
8,370,691 →
Application:
13/299,507 →
Method, Apparatus, and System for Pre-Authentication and Keep-Authentication of Content Protected Ports
Configuring Multiple Programmable Logic Devices with Serial Peripheral Interfaces
Patent:
8,384,427 →
Application:
12/752,455 →
Pre-Configuration Programmability of I/O Circuitry
Patent:
8,384,428 →
Application:
13/006,622 →
Method and System for Improving Serial Port Memory Communication Latency and Reliability
Flexible Updating of Multi-Bit Registers
Patent:
8,441,284 →
Application:
13/154,885 →
Delaying Data Signals
Patent:
8,441,292 →
Application:
12/813,573 →
Dual-Port Sram with Bit Line Clamping
Patent:
8,451,679 →
Application:
13/212,121 →
Signaling for Transitions Between Modes of Data Transmission
Low-Power Configurable Delay Element
Patent:
8,461,894 →
Application:
13/585,142 →
Digital Signal Processing Block Architecture for Programmable Logic Device
Patent:
8,463,832 →
Application:
12/146,042 →
Network Repository for Metadata
Triggered Sense Amplifier
Patent:
8,477,549 →
Application:
12/976,520 →
Adaptive Interconnection Scheme for Multimedia Devices
Alignment Circuit for Parallel Data Streams
Patent:
8,495,264 →
Application:
13/178,536 →
Discovery of Electronic Devices in a Combined Network
Hybrid Interface for Serial and Parallel Communication
Blocking Memory Readback In A Programmable Logic Device
Patent:
8,522,126 →
Application:
12/977,011 →
Phase Locked Loop Circuit with Selectable Feedback Paths
Patent:
8,531,222 →
Application:
13/079,595 →
Combining Video Data Streams of Differing Dimensionality for Concurrent Display
Simultaneous Development of Complementary Ic Families
Patent:
8,539,409 →
Application:
13/178,599 →
Voltage Regulators with a Shared Capacitor
Patent:
8,547,075 →
Application:
13/155,547 →
Voltage Discharge Circuit Having Divided Discharge Current
Patent:
8,553,463 →
Application:
13/052,142 →
Integrated Circuit Design Software with Cross Probing Between Tool Graphical User Interfaces (Guis)
Patent:
8,555,217 →
Application:
13/164,108 →
System, Method, and Apparatus for Smoothing of Edges in Images to Remove Irregularities
Smart scalable storage switch architecture
On Screen Displays Associated with Remote Video Source Devices
Determining and Configuring a Communication Path in a Network
Multi-View Display System
Integrated Circuit Package with Input Capacitance Compensation
Patent:
8,643,168 →
Application:
13/685,385 →
Placing Integrated Circuits into Low Voltage Mode for Standby Purposes
Patent:
8,643,398 →
Application:
13/680,947 →
Messaging to Provide Data Link Integrity
Method, Apparatus, and System for Deciphering Media Content Stream
Delaying Data Signals
Low-Voltage Current Sense Amplifier
Patent:
8,654,600 →
Application:
13/037,703 →
Bondwire Configuration for Reduced Crosstalk
Patent:
8,664,774 →
Application:
12/757,087 →
In-System Margin Measurement Circuit
Patent:
8,686,773 →
Application:
13/721,867 →
Video Frame Synchronization
Mechanism for Memory Reduction in Picture-in-Picture Video Generation
Triple-Trim Reference Voltage Generator
Patent:
8,710,898 →
Application:
13/653,827 →
Hybrid Interface for Serial and Parallel Communication
Transmission and Detection of Multi-Channel Signals in Reduced Channel Format
Configurable Multi-Dimensional Driver and Receiver
Integrated Circuit with Pin for Setting Digital Address
Patent:
8,786,482 →
Application:
13/857,919 →
Method, Apparatus and System for Communicating Sideband Data with Non-Compressed Video
Patent:
8,786,776 →
Application:
13/891,842 →
Detection of Encryption Utilizing Error Detection for Received Data
Hybrid H-Bridge and Cml Driver
Patent:
8,797,064 →
Application:
13/738,265 →
Discovery of Electronic Devices in a Combined Network
Variable Response Mode for Synchronous Data Read
Patent:
8,816,718 →
Application:
13/038,270 →
In-System Reconfigurable Circuit for Mapping Data Words of Different Lengths
Patent:
8,823,561 →
Application:
13/452,060 →
Dynamic Power Supply Switching for Clocking Signals
Patent:
8,829,944 →
Application:
14/040,955 →
Test Solution for Ring Oscillators
Mechanism for Memory Reduction in Picture-in-Picture Video Generation
Congestion Estimation Based on Routing Resources of Programmable Logic Devices
Patent:
8,856,718 →
Application:
12/337,502 →
Interfacing Between Integrated Circuits with Asymmetric Voltage Swing
Method and System for Improving Serial Port Memory Communication Latency and Reliability
Serializer with Multiple Stages
Patent:
8,912,933 →
Application:
13/616,173 →
Automated Service Discovery and Dynamic Connection Management
Mechanism for Facilitating Synchronization of Audio and Video Between Multiple Media Devices
Mechanism for Internal Processing of Content Through Partial Authentication on Secondary Channel
Mechanism for Facilitating Dynamic Phase Detection with High Jitter Tolerance for Images of Media Streams
Simultaneous Transmission of Clock and Bidirectional Data Over a Communication Channel
Identification and Handling of Data Streams Using Coded Preambles
Dual-Port Sram with Bit Line Clamping
Programmable Logic Device Data Rate Booster for Digital Signal Processing
Patent:
8,977,885 →
Application:
13/412,408 →
Highly Secure and Extensive Scan Testing of Integrated Circuits
Communicating with MIPI-Compliant Devices Using Non-MIPI Interfaces
Patent:
9,009,379 →
Application:
14/223,096 →
Mechanism for Low Power Standby Mode Control Circuit
Bi-Directional Digital Interface for Video and Audio (Diva)
Single-Ended Configurable Multi-Mode Driver
Simultaneous Transmission of Clock and Bidirectional Data Over a Communication Channel
Transmission of Multiple Protocol Data Elements via an Interface Utilizing a Data Tunnel
Elements to Counter Transmitter Circuit Performance Limitations
Method, Apparatus, and System for Pre-Authentication and Processing of Data Streams
Incrementer Absorption into Multiplier Logic for Programmable Logic Devices
Patent:
9,152,753 →
Application:
14/319,481 →
Group Based Routing in Programmable Logic Device
Mechanism for Facilitating Fine-Grained Self-Refresh Control for Dynamic Memory Devices
Collector Current Driver for a Bipolar Junction Transistor Temperature Transducer
Leakage-Current Abatement Circuitry for Memory Arrays
Encoding Guard Band Data For Transmission Via A Communications Interface Utilizing Transition-Minimized Differential Signaling (Tmds) Coding
Loss of Signal Detection for High-Speed Serial Links
Smart Scalable Storage Switch Architecture
Messaging to Provide Data Link Integrity
On Screen Displays Associated with Remote Video Source Devices
Full-Frame Buffer to Improve Video Performance in Low-Latency Video Communication Systems
Charge Pump Calibration for Dual-Path Phase-Locked Loop
Apparatus, System and Method for Providing Clock and Data Signaling
Low-Voltage Current Sense Amplifer
Test Solution for a Random Number Generator
Single-Ended Configurable Multi-Mode Driver
Apparatus, Method and System for Asymmetric, Full-Duplex Communication
Audio and Video Data Multiplexing for Multimedia Stream Switch
Shared Logic for Multiple Registers with Asynchronous Initialization
Radio Frequency Interference Reduction In Multimedia Interfaces
Formatting Audio-Video Information Compliant with First Transmission Format to Second Transmission Format in Integrated Circuit for Offloading Physical Layer Logic for First Transmission Format to Separate Integrated Circuit
Calibration of Single-Ended High-Speed Interfaces
Configurable Multi-Dimensional Driver and Receiver
Sram with Two-Level Voltage Regulator
PVT Compensation Scheme for Output Buffers
Method and Apparatus for Implementing Wide Data Range and Wide Common-Mode Receivers
System, Method, and Apparatus for Smoothing of Edges in Images to Remove Irregularities
Configurable Single-Ended Driver
Frequency Response Compensation in a Digital to Analog Converter
Programmable Filter
Patent:
9,325,302 →
Application:
14/558,851 →
Holdtime Correction Using Input/Output Block Delay
Line Driver with Separate Pre-Driver for Feed-Through Capacitance
Partially Depopulated Interconnection Arrays for Packaged Semiconductor Devices and Printed Circuit Boards
Compensation Scheme for Mhl Common Mode Clock Swing
Logic Absorption Techniques for Programmable Logic Devices
Bus-Based Clock to Out Path Optimization
Mechanism for Facilitating Dynamic Phase Detection with High Jitter Tolerance for Images of Media Streams
Apparatus, System and Method for Providing Switching with a T-Coil Circuit
Class Ab Amplifier with Programmable Quiescent Current
Elements to Counter Transmitter Circuit Performance Limitations
Conversion of Multimedia Data Streams for Use by Connected Devices
Combining Video and Audio Streams Utilizing Pixel Repetition Bandwidth
Authentication Engine and Stream Cipher Engine Sharing in Digital Content Protection Architectures
Semiconductor Defect Characterization
Partition Based Design Implementation for Programmable Logic Devices
Proxy Device Operation in Command and Control Network
Linear Regulator with Improved Power Supply Ripple Rejection
Multiple Protocol Tunneling Using Time Division Operations
Techniques for Fractional-N Phase Locked Loops
High-Resolution Oscillator Having Wide Frequency Range
Patent:
9,490,778 →
Application:
14/797,206 →
Phase Relationship Control for Control Channel of a Multimedia Communication Link
Simultaneous Transmission of Clock and Bidirectional Data Over a Communication Channel
HDMI Connector
Methods and Apparatuses to Provide an Electro-Optical Alignment
Control Target Selection
Mechanism for Facilitating Dynamic Counter Synchronization and Packetization in High-Definition Multimedia Interface and Mobile High-Definition Link
Hot-Socket Circuitry
Multimedia I/O System Architecture for Advanced Digital Television
Calibration of Single-Ended High-Speed Interfaces
Adaptive Technique for Adjusting Signal Development Across Bit Lines for Read Operation Robustness in Memory Circuits
Patent:
9,530,486 →
Application:
14/876,862 →
Transistor Matching for Generation of Precise Current Ratios
Esd Protection Using Shared Rc Trigger
Transmitting Multiple Differential Signals Over a Reduced Number of Physical Channels
Retry Disparity for Control Channel of a Multimedia Communication Link
Leakage-Current Abatement Circuitry for Memory Arrays
High Speed Complementary Nmos Lut Logic
Communication of Multimedia Data Streams over Multiple Communication Lanes
Electrical Duplex to Optical Conversion
Caching of Capabilities Information of Counterpart Device for Efficient Handshaking Operation
Stable Supply-Side Reference Over Extended Voltage Range With Hot-Plugging Compatibility
Phase Locked Loop with Sub-harmonic Locking Prevention Functionality
Registers for Post Configuration Testing of Programmable Logic Devices
Mixed-Width Memory Techniques for Programmable Logic Devices
Stream Creation with Limited Topology Information
Communication Bridging Between Devices via Multiple Bridge Elements
Stream Creation with Limited Topology Information
Transmission and Detection of Multi-Channel Signals in Reduced Channel Format
Communicating with MIPI-Compliant Devices Using Non-MIPI Interfaces
Programmable Circuits for Correcting Scan-Test Circuitry Defects in Integrated Circuit Designs
Secure Internal Control for Encrypting Video Data
Mechanism for Partial Encryption of Data Streams
Network Topology Discovery
Clock Placement for Programmable Logic Devices
Early Global Set/Reset Signal Determination for Programmable Logic Devices
Patent:
9,680,475 →
Application:
15/073,583 →
Stream Creation with Limited Topology Information
Crowbar Current Elimination
Delay Specific Routings for Programmable Logic Devices
Multi-View Display System
Configuration of Selected Modules of a Hardware Block Within a Programmable Logic Device
Multiple Mode Device Implementation for Programmable Logic Devices
Configuration Sequence for Programmable Logic Device
Embedded Memory Testing Using Back-To-Back Write/Read Operations
Flexible Ripple Mode Device Implementation for Programmable Logic Devices
Integrated Mobile Desktop
System-Level Dual-Boot Capability in Systems Having One or More Devices Without Native Dual-Boot Capability
Communication of Multimedia Data Streams Over Multiple Communication Lanes
Compressed Blanking Period Transfer Over a Multimedia Link
Arbitration Signaling Within a Multimedia High Definition Link (Mhl 3) Device
Hotswap Operations for Programmable Logic Devices
Multi-Channel Transmitter Synchronization Circuitry
Patent:
9,819,478 →
Application:
13/681,782 →
Partially Depopulated Interconnection Arrays for Packaged Semiconductor Devices and Printed Circuit Boards
Efficient Constant Multiplier Implementation for Programmable Logic Devices
Area-Efficient Memory Mapping Techniques for Programmable Logic Devices
Transmitting Apparatus with Source Termination
Timing Based Corrector for Video
Method for Synchronizing A/V Streams
Serdes Interface Architecture for Multi-Processor Systems
Network Repository for Metadata
Spectrum Shaping Voltage to Current Converter
Displaying Multiple Videos on Sink Device Using Display Information of Source Device
Multiplexer Reduction for Programmable Logic Devices
Compressed Blanking Period Transfer Over a Multimedia Link
Inter-Device Conflict Resolution on a Multimedia Link
Port Processor Capable of Performing Authentication for Multiple Source Devices
Method and System for Improving Serial Port Memory Communication Latency and Reliability
Selective Power Gating of Routing Resource Configuration Memory Bits for Programmable Logic Devices
Patent:
10,079,054 →
Application:
15/614,419 →
Stream Creation With Limited Topology Information
Secure Internal Control for Encrypting Video Data
Maintaining Synchronization of Encryption Process Across Devices By Sending Frame Numbers
Multiple Mode Device Implementation for Programmable Logic Devices
Clock Recovery and Data Recovery for Programmable Logic Devices
Stream Creation with Limited Topology Information
Segmented Error Coding for Block-Based Memory
Method of Transmitting and Receiving Audio Signals and Apparatus Thereof
Multi-Time Programmable Non-Volatile Memory Cell
Component Placement with Repacking for Programmable Logic Devices
Methods and Devices for Data Demodulation
Determining Oversampled Data to Be Included in Unit Intervals
Passive Equalizer with Negative Impedance to Increase a Gain
Parameter Scanning for Signal Over-Sampling
Adaptive Equalizer for Use with Clock and Data Recovery Circuit of Serial Communication Link
Method, Apparatus, and System for Automatic Data Aligner for Multiple Serial Receivers
Method, Apparatus and System for Generating and Facilitating Mobile High-Definition Multimedia Interface
Transmission of Alternative Content Over Standard Device Connectors
Conversion and Processing of Deep Color Video in a Single Clock Domain
Adjustment of Clock Signals Regenerated from a Data Stream
Multimedia Link Having a Plug and a Receptacle with a Power Line Configured as a Signal Return Path
Successive Approximation Register-based Analog-to-Digital Converter with Increased Time Frame for Digital-to-Analog Capacitor Settling
Calibration for Echo Cancellation in a Full Duplex Communication System
Enhanced Echo Cancellation in Full-Duplex Communication
Calibration for Echo Cancellation in a Full Duplex Communication System
Transmitter Circuit Harvesting Power from Power Supply of a Receiver Circuit
Method and System for Transmitting or Receiving N-Bit Video Data Over a Serial Link
Multi-Feature Gaze Tracking System and Method
Patent:
10,061,383 →
Application:
15/268,129 →
Echo Cancellation for High Speed Full Duplex Data Transmissions
Replica Cascode Bias Voltage-Controlled Oscillators
Transmission And Detection Of Multi-Channel Signals In Reduced Channel Format
Digital Content Protection Over Audio Return Data Link
Spectrum Shaping Voltage to Current Converter
System for Dynamic Audio Visual Capabilities Exchange
Line Driver Apparatus with Combined Feed-Through Capacitance and Feed-Forward Equalization
System and Methods for Device Interaction Using a Pointing Device and Attention Sensing Device
Method of Transmitting and Receiving Audio Signals and Apparatus Thereof
System and Apparatus for Gaze Tracking
System and Method for Interacting with and Analyzing Media on a Display Using Eye Gaze Tracking
Reconfigurable and Scalable Hardware Management Architecture
Clock Recovery and Data Recovery for Programmable Logic Devices
Hysteresis Control Systems and Methods for Programmable Logic Devices
Flexible Ripple Mode Device Implementation for Programmable Logic Devices
Deterministic Read Back and Error Detection for Programmable Logic Devices
Low-Speed Bus Time Stamp Methods and Circuitry
Polarization converter systems and methods
Patent:
10,484,036 →
Application:
15/999,631 →
Polarization Filter Systems and Methods
Patent:
10,484,117 →
Application:
16/103,720 →
Direct Digital Synthesis Systems and Methods
Memory Circuit Having Non-Volatile Memory Cell and Methods of Using
Multiple Mode Device Implementation for Programmable Logic Devices
Multimedia Communication Bridge
Reconfigurable and Scalable Hardware Management Architecture
Acoustic Gesture Recognition Systems and Methods
Auto-Compensation for Control Voltage Range of Vco at Low Power Supply
Low-Speed Bus Triggering Method and Circuitry
Method for Estimating User Eye Orientation Using a System-Independent Learned Mapping
Patent:
10,902,628 →
Application:
16/449,191 →
Transmitting Common Mode Control Data Over Audio Return Channel
Network Repository for Metadata
Transmission And Detection Of Multi-Channel Signals In Reduced Channel Format
Fast Boot Systems and Methods for Programmable Logic Devices
Input/Output Bus Protection Systems and Methods for Programmable Logic Devices
Transmitting Common Mode Control Data Over Audio Return Channel
Multi-Time Programmable Non-Volatile Memory Cell
Power Supply Regulation for Programmable Logic Devices
Methods and Apparatus for Estimating Point-of-Gaze in Three Dimensions
System and Method for Analyzing Three-Dimensional (3D) Media Content
System and Method for Probabilistic Object Tracking Over Time
Methods and Apparatus for Estimating Point-of-Gaze in Three Dimensions
System and Method for On-Axis Eye Gaze Tracking
System and Method For Calibrating Eye Gaze Data
Programmable Signal Routing Systems Having Low Static Leakage
Patent:
45,200 →
Application:
13/764,221 →
Memory Circuit Having Non-Volatile Memory Cell and Methods of Using
Patent:
48,570 →
Application:
16/267,278 →
Memory Circuit Having Non-Volatile Memory Cell and Methods of Using
Patent:
48,625 →
Application:
15/975,506 →
Adaptive Processing of Video Streams with Reduced Color Resolution
Patent:
48,740 →
Application:
16/460,966 →
Adaptive Processing of Video Streams with Reduced Color Resolution
Patent:
48,920 →
Application:
16/459,538 →
Test Clock Control Structures to Generate Configurable Test Clocks for Scan-Based Testing of Electronic Circuits Using Programmable Test Clock Controllers
Multimedia Communication Bridge
System and Methods for Device Interaction Using a Pointing Device and Attention Sensing Device
Programmable Linear-Feedback Shift Register Systems and Methods
Fast Boot Systems and Methods for Programmable Logic Devices
Fast Boot Systems and Methods for Programmable Logic Devices
Adaptive Power-on-Reset Generator Systems and Methods for Programmable Logic Devices
Asset Management Systems and Methods for Programmable Logic Devices
Failure Characterization Systems and Methods for Erasing and Debugging Programmable Logic Devices
Fast Boot Systems and Methods for Programmable Logic Devices
Secure Boot Systems and Methods for Programmable Logic Devices
Key Provisioning Systems and Methods for Programmable Logic Devices
Programmable Look-Up Table Systems and Methods
Information Leakage Mitigation Associated with Elliptic Curve Operations
Remote Programming Systems and Methods for Programmable Logic Devices
Selectively Powered Embedded Memory Systems and Methods
Programmable Linear-Feedback Shift Register Systems and Methods
Multi-Chip Secure and Programmable Systems and Methods
Cryptographic Hardware Sharing Systems and Methods
Dual Power Supplied Memory Cells and Deterministic Reset Thereof for Programmable Logic Devices
System and Methods for Enhanced Videoconferencing
Scalable Data Structure for Aggregating Bmc Input and Output Over Serdes for Data Center and Server Nodes System and Method
Low Latency Interrupt Alerts for Artificial Neural Network Systems and Methods in Data Stream Processing
Multi-Mode Look-Up Table with Flexible Routing for Programmable Logic Device Systems and Methods
Clock Insertion Delay Systems and Methods
Serdes Lane Control Bonding Systems and Methods
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jun 25, 2004
From: ADAMS, DALE R.
To: ANCHOR BAY TECHNOLOGIES, INC.
Reel/Frame 015496/0886 →
Assignment of Assignor's Interest
Apr 5, 2005
From: MUSIC, WAYNE D.
To: LATTICE SEMICONDUCTOR INC.
Reel/Frame 016027/0412 →
Assignment of Assignor's Interest
Feb 22, 2006
From: TANG, HOWARD; SHEN, JU; KOW, SAN-TA
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 017203/0132 →
Corrective Assignment to Correct the Doc. Date for Second Inventor Shen, Ju Should Read as 02/07/2006 as Shown on the Signed Assignmnet Document. Previously Recorded on Reel 017203 Frame 0132. Assignor(S) Hereby Confirms the Originally Filed Recordation Sheet Indicated the Doc. Date: 01/30/2006 for Shen, Ju. Please Correct to Read as 2/07/06..
Mar 2, 2006
From: TANG, HOWARD; SHEN, JU; KOW, SAN-TA
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 017244/0308 →
Assignment of Assignor's Interest
Mar 8, 2006
From: MILLER, EDWARD E.
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 017277/0133 →
Assignment of Assignor's Interest
Apr 10, 2006
From: LI, DONGHUI; PENG, JACK ZEZHONG; CHEN, JASON
To: KLP INTERNATIONAL LTD.
Reel/Frame 017775/0607 →
Assignment of Assignor's Interest
Jun 12, 2006
From: AGRAWAL, OM P.; HE, XIAOJIE; WIJESURIYA, SAJITHA; BRITTON, BARRY
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 017763/0385 →
Assignment of Assignor's Interest
Jun 28, 2006
From: TANG, HOWARD; AGRAWAL, OM P.; RUTLEDGE, DAVID L.; FONTANA, FABIANO
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 017855/0056 →
Assignment of Assignor's Interest
Jun 28, 2006
From: AGRAWAL, OM P.; HE, XIAOJIE; WIJESURIYA, SAJITHA; BRITTON, BARRY
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 017854/0634 →
Assignment of Assignor's Interest
Jun 28, 2006
From: AGRAWAL, OM P.; BRITTON, BARRY; HE, XIAOJIE; WIJESURIYA, SAJITHA
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 017854/0428 →
Assignment of Assignor's Interest
Jul 11, 2006
From: HAZANCHUK, ASHER; ING, IAN; SINGH, SATWANT
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 017912/0910 →
Assignment of Assignor's Interest
Jul 13, 2006
From: RUTLEDGE, DAVID L.; HAN, WEI; YERRAMILLI, YOSHITA
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 017928/0078 →
Assignment of Assignor's Interest
Jan 4, 2007
From: ANDREWS, WILLIAM B.; LIN, MON C.; SCHADT, JOHN A.
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 018724/0283 →
Assignment of Assignor's Interest
Jan 8, 2007
From: FENSTERMAKER, LARRY R.; SCHOLZ, HAROLD
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 018765/0140 →
Assignment of Assignor's Interest
Oct 31, 2007
From: GREEN, NATHAN ROBERT; MCLAURY, LOREN L.
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 020044/0325 →
Assignment of Assignor's Interest
Dec 7, 2010
From: ANCHOR BAY TECHNOLOGIES, INC.
To: ABT-AC, INC.
Reel/Frame 025461/0563 →
Assignment of Assignor's Interest
Feb 16, 2011
From: ABT-AC, INC.
To: SILICON IMAGE, INC.
Reel/Frame 025818/0387 →
Change of Name
Mar 15, 2012
From: KLP INTERNATIONAL LTD.
To: SILICONBLUE TECHNOLOGIES LTD.
Reel/Frame 027873/0368 →
Merger
Apr 9, 2012
From: SILCONBLUE TECHNOLOGIES LTD.
To: LATTICE SEMICONDUCTOR LIMITED
Reel/Frame 028011/0951 →
Assignment of Assignor's Interest
Mar 6, 2015
From: LATTICE SEMICONDUCTOR LIMITED
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 035101/0559 →
Security Interest
Mar 18, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035223/0001 →
Security Interest
Mar 19, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035226/0289 →
Security Interest
Mar 24, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC; SILICON IMAGE, INC.; DVDO, INC.
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Security Interest
Mar 24, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035309/0142 →
Merger
Aug 21, 2015
From: SILICON IMAGE, INC.
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 036419/0792 →