SCALABLE DATA STRUCTURE FOR AGGREGATING BMC INPUT AND OUTPUT OVER SERDES FOR DATA CENTER AND SERVER NODES SYSTEM AND METHOD
A system, method, and computer program product for communicating between a baseboard management controller (BMC) and a host processing module (HPM) are provided. A PCIe endpoint receives packets, such as TLPs, over a first communication interface from a BMC, where payloads in packets include transactions. The PCIe endpoint extracts the transactions from the payloads of packets. An address decoder decodes, using information in the transactions, addresses of the memory spaces corresponding to physical functions of the PCIe endpoint and second communication interfaces. The memory spaces store the transactions according to the decoded addresses. The second communication interface receives the transactions from the memory spaces and transmits the transactions to the HPM.
1 . (canceled)
2 . A method comprising:
communicating transactions using a plurality of first communication interfaces from a host processing module (HPM) to a port expansion field programmable gate array (FPGA);
storing the transactions in a plurality of memory spaces within the FPGA, the plurality of memory spaces corresponding to the plurality of first communication interfaces;
encoding, using information in the transactions, the transactions in the plurality of memory spaces to corresponding physical functions of an endpoint;
generating a plurality of transaction layer packets (TLPs) that include the transactions in payloads of the TLPs; and
communicating, from the endpoint of the port expansion FPGA to a baseboard management controller (BMC), the TLPs over a second communication interface.
3 . The method of claim 2 , wherein the endpoint is a Peripheral Component Interconnect Express (PCIe) endpoint and the second communication interface is a PCIe interface.
4 . The method of claim 2 , wherein the plurality of first communication interfaces are Low-Voltage Differential Signaling (LVDS) tunneling protocol interface (LTPI IP) interfaces having different formats.
5 . The method of claim 4 , wherein the plurality of communication interfaces comprise one or more of an Inter-Integrated Circuit (I2C) interface, a universal asynchronous receiver/transmitter (UART) interface, and a general purpose input/output (GPIO) interface.
6 . The method of claim 2 , wherein the plurality of memory spaces are implemented as a memory-mapped I/O (MMIO) or a first-in, first-out (FIFO) memory spaces.
7 . The method of claim 2 , wherein a physical function in plurality of physical functions corresponds to at least two addresses in the plurality of memory spaces.
8 . The method of claim 2 , wherein a plurality of physical functions and the plurality of first communication interfaces correspond to interface identifiers included in the transactions.
9 . The method of claim 8 , wherein a physical function in the plurality of physical functions corresponds to at least two interface identifiers.
10 . The method of claim 8 , wherein the interface identifiers and the plurality of first communication interfaces are assigned corresponding priorities for communicating the transactions from the HPM.
11 . The method of claim 2 , wherein a payload of a TLP in the plurality of TLPs includes a transaction formatted into a data structure, and wherein the data structure includes at least a virtual interface identifier field, an interface type field, a completion code field, a length field, and a payload field.
12 . A system comprising:
a plurality of first communication interfaces configured to receive transactions from a host processing module (HPM);
a plurality of memory spaces configured to store the transactions, wherein each memory space corresponds to one or more of the plurality of first communication interfaces;
an address decoder configured to encode, using information in the transactions, the transactions in the plurality of memory spaces to corresponding physical functions of an endpoint; and
the endpoint configured to:
generate a plurality of transaction layer packets (TLPs) that include the transactions in payloads of the TLPs; and
communicate the TLPs to a baseboard management controller (BMC) over a second communication interface.
13 . The system of claim 12 , wherein the endpoint is a Peripheral Component Interconnect Express (PCIe) endpoint and the second communication interface is a PCIe interface.
14 . The system of claim 12 , wherein the system is a port expansion field programmable gate array (FPGA).
15 . The system of claim 12 , wherein the plurality of first communication interfaces are Low-Voltage Differential Signaling (LVDS) tunneling protocol interface (LTPI IP) interfaces having different formats.
16 . The system of claim 12 , wherein the plurality of memory spaces are implemented as a memory-mapped I/O (MMIO) or a first-in, first-out (FIFO) memory spaces.
17 . The system of claim 12 , wherein a physical function in plurality of physical functions corresponds to at least two addresses in the plurality of memory spaces.
18 . The system of claim 12 , wherein a plurality of physical functions and the plurality of first communication interfaces correspond to interface identifiers included in the transactions.
19 . The system of claim 18 , wherein a physical function in the plurality of physical functions corresponds to at least two interface identifiers.
20 . The system of claim 18 , wherein the interface identifiers and the plurality of first communication interfaces are assigned corresponding priorities for communicating the transactions from the HPM.
21 . A host processing module (HPM) comprising:
a plurality of input/output (I/O) interfaces configured to communicate transactions to a port expansion field programmable gate array (FPGA), wherein the plurality of I/O interfaces are in different formats;
wherein the transactions are configured to be:
stored in a plurality of memory spaces of the port expansion FPGA corresponding to the plurality of I/O interfaces;
encoded, using information in the transactions, to corresponding physical functions of an endpoint of the port expansion FPGA; and
included in payloads of a plurality of transaction layer packets (TLPs) for communication to a baseboard management controller (BMC) over a second communication interface.