IP Library Granted Patent US 12,645,385
Granted Patent B2
US 12,645,385 · App. 18/526,103 · Granted Jun 2, 2026

Providing recovered data to a new memory cell at a memory sub-system based on an unsuccessful error correction operation

Inventors: Sampath K. Ratnam (San Jose, CA); Vamsi Pavan Rayaprolu (Santa Clara, CA); Mustafa N. Kaynak (San Diego, CA); Sivagnanam Parthasarathy (Carlsbad, CA); Kishore Kumar Muchherla (San Jose, CA); Shane Nowell (Boise, ID); Peter Feeley (Boise, ID); Qisong Lin (El Dorado Hills, CA)
Assignee: Micron Technology, Inc.
G06F3/0647G06F3/0619G06F3/0673G06F11/1068G06F11/1402G11C29/52
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,645,385
App. No.
18/526,103
Granted
Jun 2, 2026
Kind
B2
Abstract

At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data is provided to the other memory cell of the memory component.

Claims (46)

1 . A system comprising:

a memory component; and

a processing device, operatively coupled with the memory component, to:

perform a first pass of a two-pass programming operation to store a set of data at a first portion of the memory component;

designate a first subset of the set of data as a proxy for estimating an error rate of a second subset of the set of data, wherein an error rate of the first subset exceeding a threshold indicates that error correction is to be performed on the second subset;

determine that the second subset of the set of data is associated with an unsuccessful error correction operation;

responsive to completing a second pass of the two-pass programming operation with respect to the second subset of the set of data, recover the second subset of the set of data.

2 . The system of claim 1 , wherein the processing device is further to:

store the second subset of the set of data at a second portion of the memory component;

receive a second set of data associated with the set of data; and

store the second set of data at the second portion of the memory component.

3 . The system of claim 2 , wherein the first portion of the memory component comprises a first block and the second portion of the memory component comprises a second block.

4 . The system of claim 1 , wherein determining that the second subset of the set of data is associated with an unsuccessful error correction operation is performed in response to performing a read operation with respect to the second subset of the set of data stored at the first portion of the memory component.

5 . The system of claim 4 , wherein the read operation is performed before the second pass of the two-pass programming operation.

6 . The system of claim 1 , wherein recovering the second subset of the set of data is based on parity data associated with the set of data.

7 . The system of claim 1 , wherein determining that the second subset of the set of data is associated with an unsuccessful error correction operation further comprises:

inspecting identification information stored in a data structure in association with the second subset of the set of data.

8 . A method, comprising:

performing, by a processing device, a first pass of a two-pass programming operation to store a set of data at a first portion of a memory component;

designating a first subset of the set of data as a proxy for estimating an error rate of a second subset of the set of data, wherein an error rate of the first subset exceeding a threshold indicates that error correction is to be performed on the second subset;

determining that the second subset of the set of data is associated with an unsuccessful error correction operation;

responsive to completing a second pass of the two-pass programming operation with respect to the second subset of the set of data, recovering the second subset of the set of data.

9 . The method of claim 8 , further comprising:

storing the second subset of the set of data at a second portion of the memory component;

receiving a second set of data associated with the set of data; and

storing the second set of data at the second portion of the memory component.

10 . The method of claim 9 , wherein the first portion of the memory component comprises a first block and the second portion of the memory component comprises a second block.

11 . The method of claim 8 , wherein determining that the second subset of the set of data is associated with an unsuccessful error correction operation is performed in response to performing a read operation with respect to the second subset of the set of data stored at the first portion of the memory component.

12 . The method of claim 11 , wherein the read operation is performed before the second pass of the two-pass programming operation.

13 . The method of claim 8 , wherein recovering the second subset of the set of data is based on parity data associated with the set of data.

14 . The method of claim 8 , wherein determining that the second subset of the set of data is associated with an unsuccessful error correction operation further comprises:

inspecting identification information stored in a data structure in association with the second subset of the set of data.

15 . A non-transitory computer-readable storage medium comprising executable instructions that, when executed by a processing device, cause the processing device to:

perform a first pass of a two-pass programming operation to store a set of data at a first portion of a memory component;

designate a first subset of the set of data as a proxy for estimating an error rate of a second subset of the set of data, wherein an error rate of the first subset exceeding a threshold indicates that error correction is to be performed on the second subset;

determine that the second subset of the set of data is associated with an unsuccessful error correction operation;

responsive to completing a second pass of the two-pass programming operation with respect to the second subset of the set of data, recover the second subset of the set of data.

16 . The non-transitory computer-readable storage medium of claim 15 , further comprising executable instructions that, when executed by the processing device, cause the processing device to:

store the second subset of the set of data at a second portion of the memory component;

receive a second set of data associated with the set of data; and

store the second set of data at the second portion of the memory component.

17 . The non-transitory computer-readable storage medium of claim 15 , wherein determining that the second subset of the set of data is associated with an unsuccessful error correction operation is performed in response to performing a read operation with respect to the second subset of the set of data stored at the first portion of the memory component.

18 . The non-transitory computer-readable storage medium of claim 17 , wherein the read operation is performed before the second pass of the two-pass programming operation.

19 . The non-transitory computer-readable storage medium of claim 15 , wherein recovering the second subset of the set of data is based on parity data associated with the set of data.

20 . The non-transitory computer-readable storage medium of claim 15 , wherein determining that the second subset of the set of data is associated with an unsuccessful error correction operation further comprises:

inspecting identification information stored in a data structure in association with the second subset of the set of data.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2024
From: RATNAM, SAMPATH K.; RAYAPROLU, VAMSI PAVAN; KAYNAK, MUSTAFA N.; PARTHASARATHY, SIVAGNANAM; MUCHHERLA, KISHORE KUMAR; NOWELL, SHANE; FEELEY, PETER; LIN, QISONG
To: MICRON TECHNOLOGY, INC.
Reel/Frame 066557/0270 →
Continuity (4)
Continuation 17350866 · Jun 17, 2021
Continuation 16100681 · Aug 10, 2018
Provisional Application 62628706 · Feb 9, 2018
Related Publication 20240103749A1 · Mar 28, 2024
References Cited (32)
US 7954037B2 · Lasser et al. · 2011 [cited by applicant]
US 8837064B1 · Wu et al. · 2014 [cited by applicant]
US 9818488B2 · Sankaranarayanan et al. · 2017 [cited by applicant]
US 10180868B2 · Alhussien et al. · 2019 [cited by applicant]
US 10540228B2 · Kaynak et al. · 2020 [cited by applicant]
US 10892029B1 · Xie et al. · 2021 [cited by applicant]
US 20090287975A1 · Kim et al. · 2009 [cited by applicant]
US 20110126045A1 · Bennett · 2011 [cited by applicant]
US 20110182121A1 · Dutta · 2011 [cited by examiner]
US 20140059406A1 · Hyun et al. · 2014 [cited by applicant]
US 20150100847A1 · Ojalvo et al. · 2015 [cited by applicant]
US 20150154089A1 · Wu et al. · 2015 [cited by applicant]
US 20150378815A1 · Goda · 2015 [cited by examiner]
US 20170062067A1 · Yang et al. · 2017 [cited by applicant]
US 20170070241A1 · Kaku et al. · 2017 [cited by applicant]
US 20170102991A1 · Haratsch · 2017 [cited by examiner]
US 20170148525A1 · Kathawala et al. · 2017 [cited by applicant]
US 20170249211A1 · Hoei et al. · 2017 [cited by applicant]
US 20180011753A1 · Alhussien et al. · 2018 [cited by applicant]
US 20180018233A1 · Kim · 2018 [cited by examiner]
US 20180293029A1 · Achtenberg et al. · 2018 [cited by applicant]
US 20190097132A1 · Rajamohanan et al. · 2019 [cited by applicant]
US 20190189202A1 · Avraham et al. · 2019 [cited by applicant]
US 20190278655A1 · Koudele et al. · 2019 [cited by applicant]
US 20200066353A1 · Pletka et al. · 2020 [cited by applicant]
US 20210012857A1 · Xie et al. · 2021 [cited by applicant]
US 20220028475A1 · Sharon · 2022 [cited by examiner]
CN 105144302A · 2015 [cited by applicant]
Cai Y., et al., “Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery,” Nov. 28, 2017, 86 Pages, arXiv: 1711.11427v2, XP081304598. [cited by applicant]
International Preliminary Report on Patentability for International Application No. PCT/US2019/016421, mailed Aug. 20, 2020, 10 Pages. [cited by applicant]
International Search Report and Written Opinion for International Application No. PCT/US2019/017333, mailed May 28, 2019, 11 Pages. [cited by applicant]
Yan S., et al., “Tiny-Tail flash: Near-Perfect Elimination of Garbage Collection Tail Latencies in NAND SSDs,” ACM Transactions on Storage (TOS), 2017, vol. 13, No. 3, 15 Pages. [cited by applicant]