Yield improvements for three-dimensionally stacked neural network accelerators
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.
1. A device comprising a plurality of stacked dies, each die comprising a plurality of tiles, wherein each tile comprises:
a processing element configured to perform one or more computations;
an inductive coil that is reconfigurable to receive data from a vertically adjacent tile of another die in the plurality of stacked dies; and
switching circuitry that is reconfigurable to select between routing input data received through the inductive coil to the processing element or routing the input data to a processing element bypass that bypasses the processing element.
2. The device of claim 1 , wherein the device has a dataflow configuration that in operation causes the tiles of the stacked dies to implement the computations of a neural network.
3. The device of claim 1 , wherein the dataflow configuration causes a first tile of a plurality of tiles of a first die to route input data to a first processing element of the first tile.
4. The device of claim 3 , wherein the dataflow configuration causes a second tile of the plurality of tiles of the first die to route input data to a processing element bypass of the second tile.
5. The device of claim 4 , wherein the dataflow configuration causes the first tile to receive the input data routed through the processing element bypass of the second tile.
6. The device of claim 5 , wherein the dataflow configuration causes a third tile of the first die to be bypassed entirely.
7. The device of claim 1 , wherein each tile comprises a pair of inductive coils that are reconfigurable to transmit or receive data from an adjacent tile of another die.
8. The device of claim 7 , wherein the pair of inductive coils are reconfigurable to transmit or receive data from a vertically adjacent tile of another die.
9. A method of routing data in device comprising a plurality of stacked dies, each die comprising a plurality of tiles, wherein each tile comprises:
a processing element configured to perform one or more computations;
an inductive coil that is reconfigurable to receive data from a vertically adjacent tile of another die in the plurality of stacked dies; and
switching circuitry that is reconfigurable to select between routing input data received through the inductive coil to the processing element or routing the input data to a processing element bypass that bypasses the processing element,
the method comprising routing, by switching circuitry of a first tile of a first die of the plurality of stacked dies in accordance with a dataflow configuration of the device, input data received by the first tile to a processing element bypass of the first tile.
10. The method of claim 9 , further comprising implementing the computations of a neural network using the plurality of stacked dies.
11. The method of claim 9 , further comprising routing, by switching circuitry of a second tile of the first die, input data to a processing element of the second tile.
12. The method of claim 11 , further comprising receiving, by the second tile, input data routed through the processing element bypass of the first tile.
13. The method of claim 9 , further comprising bypassing a third tile of the first die in accordance with the dataflow configuration.
14. The method of claim 9 , wherein each tile comprises a pair of inductive coils that are reconfigurable to transmit or receive data from an adjacent tile of another die.
15. The method of claim 14 , wherein the pair of inductive coils are reconfigurable to transmit or receive data from a vertically adjacent tile of another die.
16. A method of reconfiguring a device comprising a plurality of stacked dies, each die comprising a plurality of tiles, wherein each tile comprises:
a processing element configured to perform one or more computations;
an inductive coil that is reconfigurable to receive data from a vertically adjacent tile of another die in the plurality of stacked dies; and
switching circuitry that is reconfigurable to select between routing input data received through the inductive coil to the processing element or routing the input data to a processing element bypass that bypasses the processing element,
the method comprising reconfiguring switching circuitry of a first tile of the plurality of tiles to route input data to a processing element bypass of the first instead of a processing element of the first tile.
17. The method of claim 16 , further comprising reconfiguring switching circuitry of a second tile of the plurality of tiles to route input data to a processing element of the second tile instead of to a processing element bypass of the second tile.