Memory, operation method of memory and memory system including read calibration circuit
A memory includes a page buffer that includes a sensing latch circuit, a first charge circuit and a read calibration circuit. The first charge circuit and the sensing latch circuit are coupled to a sensing node, and the read calibration circuit is coupled to the sensing latch circuit at a first end and to the sensing node at a second end, and is configured to calibrate a potential of the sensing node during sensing. The above-mentioned memory is applied in a calibration process of the potential of the sensing node during sensing.
1 . A memory, comprising:
a page buffer comprising:
a sensing latch circuit;
a first charge circuit coupled to a sensing node; and
a read calibration circuit, a first end of the read calibration circuit being coupled to the sensing latch circuit and a second end of the read calibration circuit being coupled to the sensing node, and the read calibration circuit being configured to calibrate a potential of the sensing node in a sensing process, wherein:
the sensing process comprises a calibration stage; and
the read calibration circuit comprises:
a first sub-circuit configured to discharge the sensing node from a first voltage value to a second voltage value in a first sub-stage of the calibration stage; and
a second sub-circuit configured to charge the sensing node from the second voltage value to a third voltage value in a second sub-stage of the calibration stage.
2 . The memory of claim 1 , wherein the first sub-circuit comprises a first transistor, a second transistor and a third transistor;
a first end of the first transistor is coupled to the first end of the read calibration circuit;
a second end of the first transistor is coupled to a first end of the third transistor;
a first end of the second transistor is coupled to the first end of the first transistor;
a second end of the second transistor and a second end of the third transistor are coupled and coupled to the second end of the read calibration circuit; and
a control end of the third transistor is coupled to ground.
3 . The memory of claim 2 , wherein:
the first transistor and the second transistor are turned on and the third transistor is cut off, in the first sub-stage of the calibration stage; and
the first transistor and the third transistor are cut off and the second transistor is turned on, in the second sub-stage of the calibration stage.
4 . The memory of claim 2 , wherein:
the sensing process further comprises a sensing stage; and
in the sensing stage, the first transistor is turned on and the second transistor is cut off.
5 . The memory of claim 1 , wherein:
the second sub-circuit comprises a capacitance and a second charge circuit;
a first end of the capacitance is coupled to the sensing node;
a second end of the capacitance is coupled a first node;
the first node is further coupled to an output end of the second charge circuit;
the second charge circuit is configured to charge the first node in the second sub-stage of the calibration stage; and
the sensing node is charged from the second voltage value to the third voltage value.
6 . The memory of claim 5 , wherein the capacitance is a stray capacitance.
7 . The memory of claim 1 , wherein the sensing latch circuit comprises: a first phase inverter, a second phase inverter, a fourth transistor, a fifth transistor and a sixth transistor;
a first end of the first phase inverter is coupled to a first end of the second phase inverter;
a second end of the first phase inverter is coupled to a second end of the second phase inverter;
a first end of the fourth transistor is coupled to the first end of the first phase inverter;
a second end of the fourth transistor is coupled to a first end of the sixth transistor;
a second end of the sixth transistor is coupled to ground;
a first end of the fifth transistor is coupled to the second end of the second phase inverter; and
a second end of the fifth transistor is coupled to the first end of the sensing latch circuit.
8 . The memory of claim 1 , wherein the page buffer further comprises an input circuit, wherein a first end of the input circuit is coupled to a bit line, and a second end of the input circuit is coupled to the sensing node.
9 . An operation method of a memory, comprising:
discharging a sensing node from a first voltage value to a second voltage value in a first sub-stage of a calibration stage;
charging the sensing node from the second voltage value to a third voltage value in a second sub-stage of the calibration stage; and
storing a state of a memory cell coupled with a bit line in a sensing stage.
10 . The method of claim 9 , wherein the charging the sensing node from the second voltage value to the third voltage value in the second sub-stage of the calibration stage comprises:
applying a first voltage to a control end of a second transistor of a read calibration circuit in the second sub-stage of the calibration stage.
11 . The method of claim 9 , wherein the charging the sensing node from the second voltage value to the third voltage value in the second sub-stage of the calibration stage comprises:
charging a first node in the second sub-stage of the calibration stage.
12 . The method of claim 9 , further comprising:
charging the sensing node to the first voltage value before the first sub-stage of the calibration stage.
13 . The method of claim 9 , further comprising:
obtaining the state of the memory cell coupled with the bit line in the sensing stage.
14 . A memory system, comprising:
one or more memories comprising:
a page buffer comprising:
a sensing latch circuit;
a first charge circuit coupled to a sensing node; and
a read calibration circuit, a first end of the read calibration circuit being coupled to the sensing latch circuit and a second end of the read calibration circuit being coupled to the sensing node, and the read calibration circuit being configured to calibrate a potential of the sensing node in a sensing process,
wherein:
the sensing process comprises a calibration stage; and
the read calibration circuit comprises:
a first sub-circuit configured to discharge the sensing node from a first voltage value to a second voltage value in a first sub-stage of the calibration stage; and
a second sub-circuit configured to charge the sensing node from the second voltage value to a third voltage value in a second sub-stage of the calibration stage; and
a memory controller coupled to the memories and configured to control the memories.
15 . The memory system of claim 14 , wherein the first sub-circuit comprises a first transistor, a second transistor and a third transistor;
a first end of the first transistor is coupled to the first end of the read calibration circuit;
a second end of the first transistor is coupled to a first end of the third transistor;
a first end of the second transistor is coupled to the first end of the first transistor;
a second end of the second transistor and a second end of the third transistor are coupled and coupled to the second end of the read calibration circuit; and
a control end of the third transistor is coupled to ground.
16 . The memory system of claim 15 , wherein:
the first transistor and the second transistor are turned on and the third transistor is cut off, in the first sub-stage of the calibration stage; and
the first transistor and the third transistor are cut off and the second transistor is turned on, in the second sub-stage of the calibration stage.
17 . The memory system of claim 15 , wherein:
the sensing process further comprises a sensing stage; and
in the sensing stage, the first transistor is turned on and the second transistor is cut off.
18 . The memory system of claim 14 , wherein:
the second sub-circuit comprises a capacitance and a second charge circuit;
a first end of the capacitance is coupled to the sensing node;
a second end of the capacitance is coupled a first node;
the first node is further coupled to an output end of the second charge circuit;
the second charge circuit is configured to charge the first node in the second sub-stage of the calibration stage; and
the sensing node is charged from the second voltage value to the third voltage value.