Semiconductor memory device having a semiconductor chip including a memory cell and a resistance element
According to one embodiment, a semiconductor device includes: a first memory cell provided in a first semiconductor chip; a first output buffer circuit configured to output data of the first memory cell outside, the first output buffer circuit provided in the first semiconductor chip; a first calibration control circuit configured to calibrate an impedance of the first output buffer circuit, a first terminal connected to the first calibration control circuit, the first calibration control circuit provided in the first semiconductor chip; and a first resistance element connected to the first terminal, the first resistance element provided in the first semiconductor chip.
1. A semiconductor device comprising:
a first memory cell provided in a first semiconductor chip;
a first output buffer circuit configured to output data of the first memory cell outside, the first output buffer circuit provided in the first semiconductor chip;
a first calibration control circuit configured to calibrate an impedance of the first output buffer circuit, a first terminal connected to the first calibration control circuit, the first calibration control circuit provided in the first semiconductor chip; and
a first resistance element connected to the first terminal, the first resistance element provided in the first semiconductor chip.
2. The semiconductor device according to claim 1 , further comprising:
a first sequencer configured to control an operation of the first memory cell, the first sequencer provided in a first semiconductor chip,
wherein when a read operation is performed for the first memory cell,
the first sequencer sets a ready/busy signal to a busy state based on a read command, and
the first calibration control circuit calibrates the impedance of the first output buffer circuit within a period in which the ready/busy signal is the busy state.
3. The semiconductor device according to claim 1 , wherein
the impedance is calibrated based on a resistance value of the first resistance element.
4. The semiconductor device according to claim 1 further comprising:
a temperature sensor configured to sense a temperature of the first semiconductor chip, the temperature sensor provided in a first semiconductor chip,
wherein the temperature sensor controls a resistance value of the first resistance element based on a sense result of the temperature.
5. The semiconductor device according to claim 1 , further comprising:
a second memory cell provided in a second semiconductor chip;
a second output buffer circuit configured to output data of the second memory cell outside, the second output buffer circuit provided in a second semiconductor chip;
a second calibration control circuit configured to calibrate an impedance of the second output buffer circuit, the second calibration control circuit provided in a second semiconductor chip;
a second terminal connected to the second calibration control circuit, the second terminal provided in a second semiconductor chip; and
a second resistance element connected to the second terminal, the second resistance element provided in the second substrate,
wherein
the first semiconductor chip is provided above a substrate,
the second semiconductor chip is provided above the first semiconductor chip, and
the first semiconductor chip and the second semiconductor chip is covered with a package material.
6. The semiconductor device according to claim 5 , wherein the first output buffer circuit and the second output buffer circuit are connected in common with a third terminal on the substrate.
7. The semiconductor device according to claim wherein the first semiconductor chip is a NAND flash memory.
8. A semiconductor device comprising:
a first memory cell provided in a first semiconductor chip above a substrate;
a first output buffer circuit configured to output data of the first memory cell outside, the first output buffer circuit provided in the first semiconductor chip;
a first calibration control circuit configured to calibrate an impedance of the first output buffer circuit, the first calibration control circuit provided in the first semiconductor chip;
a first terminal connected to the first calibration control circuit, the first terminal provided on the first semiconductor chip; and
a second memory cell provided in a second semiconductor chip, the second semiconductor chip above the first semiconductor chip;
a second output buffer circuit configured to output data of the second memory cell outside, the second output buffer circuit provided in the second semiconductor chip;
a second calibration control circuit configured to calibrate an impedance of the second output buffer circuit, the second calibration control circuit provided in the second semiconductor chip;
a second terminal connected to the second calibration control circuit, the second terminal provided in the second semiconductor chip;
a first resistance element provided in the substrate and connected to the first terminal;
a second resistance element provided in the substrate and connected to the second terminal,
wherein the first semiconductor chip and the second semiconductor chip is covered with a package material.
9. The semiconductor device according to claim 8 , further comprising:
a first sequencer configured to control an operation of the first memory cell, the first sequencer provided in the first semiconductor chip,
wherein when a read operation is performed for the first memory cell,
the first sequencer sets a ready/busy signal to a busy state based on a read command, and
the first calibration control circuit calibrates the impedance of the first output buffer circuit within a period in which the ready/busy signal is the busy state.
10. The semiconductor device according to claim 9 , wherein
the impedance is calibrated based on a resistance value of the first resistance element.
11. The semiconductor device according to claim 8 , further comprising:
a temperature sensor configured to sense a temperature of the first semiconductor chip, the temperature sensor provided in the first semiconductor chip, and
wherein the temperature sensor controls a resistance value of the first resistance element based on a sense result of the temperature.
12. The semiconductor device according to claim 8 , wherein
the first output buffer circuit and the second output buffer circuit are connected in common with a third terminal on the substrate.
13. The semiconductor device according to claim 8 , wherein the first semiconductor chip is a NAND flash memory chip.
14. A semiconductor device comprising:
a first memory cell provided in a first semiconductor chip;
a first output buffer circuit configured to output data of the first memory cell outside, the first output buffer circuit provided in the first semiconductor chip;
a first calibration control circuit configured to calibrate an impedance of the first output buffer circuit, the first calibration control circuit provided in the first semiconductor chip; and
a first resistance element connected to the first calibration control circuit, the first resistance element provided in the first semiconductor chip.
15. The semiconductor device according to claim 14 , further comprising:
a first sequencer configured to control an operation of the first memory cell, the first sequencer provided in the first semiconductor chip,
wherein when a read operation is performed for the first memory cell,
the first sequencer sets a ready/busy signal to a busy state based on a read command, and
the first calibration control circuit calibrates the impedance of the first output buffer circuit within a period in which the ready/busy signal is the busy state.
16. The semiconductor device according to claim 15 , wherein
the impedance is calibrated based on a resistance value of the resistance element.
17. The semiconductor device according to claim 14 , further comprising:
a temperature sensor configured to sense a temperature of the first semiconductor chip, the temperature sensor provided in the first semiconductor chip,
wherein the temperature sensor controls a resistance value of the first resistance element based on a sense result of the temperature.
18. The semiconductor device according to claim 14 , further comprising:
a second memory cell provided in a second semiconductor chip;
a second output buffer circuit configured to output data of the second memory cell outside, the second output buffer circuit provided in the second semiconductor chip;
a second calibration control circuit configured to calibrate an impedance of the second output buffer circuit, the second calibration control circuit provided in the second semiconductor chip; and
a second resistance element connected to the second calibration control circuit, the second resistance element provided in the second semiconductor chip,
wherein the first semiconductor chip is provided above a substrate,
the second semiconductor chip is provided above the first semiconductor chip,
the first semiconductor chip and the second semiconductor chip is covered with a package material, and
the first output buffer circuit and the second output buffer circuit are connected in common with a third terminal on the substrate.
19. The semiconductor device according to claim 14 , wherein the first semiconductor chip is a NAND flash memory chip.