Integration of a vertical diode and a transistor
A semiconductor integrated circuit (IC) device includes both a transistor and a vertical diode. In some examples, the transistor includes a backside source/drain (S/D) contact and the vertical diode includes a backside bottom contact. The backside S/D contact and the backside bottom contact may be electrically connected to a backside BEOL network. The transistor may further include a S/D region that includes an upper S/D portion and a trench S/D portion that has a higher dopant concentration relative to the upper portion. The backside S/D contact may be connected to the trench S/D portion of the S/D region. The vertical diode may include a bottom doped region which may be simultaneously formed along with the trench S/D portion and may be composed of substantially the same materials. The backside bottom contact may be directly connected to the bottom doped region of the vertical diode.
1 . A semiconductor integrated circuit (IC) device comprising:
a transistor comprising a first p-doped source/drain (S/D) region, a second p-doped S/D region, one or more channels between the first p-doped S/D region and the second p-doped S/D region, a gate around the one or more channels, and a p-doped trench S/D region below and connected to the first p-doped S/D region; and
a vertical diode comprising an intrinsic semiconductor region between a top n-doped diode region and a bottom p-doped diode region.
2 . The semiconductor IC device of claim 1 , wherein the p-doped trench S/D region and the bottom p-doped diode region are both composed of a semiconductor material and a dopant.
3 . The semiconductor IC device of claim 2 , wherein a concentration of the dopant within the p-doped trench S/D region is substantially the same as a concentration of the dopant within the bottom p-doped diode region.
4 . The semiconductor IC device of claim 1 , wherein a top surface of the bottom p-doped diode region is below a bottom surface of the p-doped trench S/D region.
5 . The semiconductor IC device of claim 1 , wherein a bottom surface of the p-doped S/D region, a bottom surface of the second p-doped S/D region, and a bottom surface of the n-doped diode region are substantially coplanar.
6 . The semiconductor IC device of claim 5 , wherein a top surface of the first p-doped S/D region, a top surface of the second p-doped S/D region, and a top surface of the n-doped diode region are substantially coplanar.
7 . The semiconductor IC device of claim 1 , further comprising:
an inactive region adjacent to the vertical diode, the inactive region comprising one or more inactive channels connected to the n-doped diode region and an inactive gate around the one or more inactive channels.
8 . The semiconductor IC device of claim 7 , wherein the one or more inactive channels are inactive because charge carriers do not flow through the one or more inactive channels.
9 . The semiconductor IC device of claim 7 , wherein the inactive gate is electrically isolated.
10 . The semiconductor IC device of claim 1 , wherein a dopant concentration within the first p-doped S/D region is less than a dopant concentration within the p-doped trench S/D region.
11 . The semiconductor IC device of claim 1 , wherein a bottom surface of the p-doped trench S/D region is below a bottom surface of the p-doped S/D region.
12 . The semiconductor IC device of claim 1 , further comprising:
a backside S/D contact connected to the p-doped trench S/D region;
a backside diode contact connected to the bottom p-doped diode region; and
a backside back end of line (BEOL) network comprising a first backside wire connected to the backside S/D contact and a second backside wire connected to the backside diode contact.
13 . The semiconductor IC device of claim 12 , further comprising:
a frontside S/D contact connected to the second S/D region;
a frontside diode contact connected to the top n-doped diode region; and
a frontside BEOL network comprising a first frontside wire electrically connected to the frontside S/D contact and a second frontside wire connected to the frontside diode contact.
14 . A semiconductor integrated circuit (IC) device comprising:
a transistor region comprising a transistor, the transistor comprising a first p-doped source/drain (S/D) region, a second p-doped S/D region, one or more channels between the first p-doped S/D region and the second p-doped S/D region, and a gate around the one or more channels, and a p-doped trench S/D region below the first p-doped S/D region; and
a diode region comprising a first vertical diode that includes a first top n-doped diode region, a second vertical diode that includes a second top n-doped diode region, a shared intrinsic semiconductor region connected to the first top n-doped diode region and to the second top n-doped diode region, and a shared bottom p-doped diode region connected to the shared intrinsic semiconductor region.
15 . The semiconductor IC device of claim 14 , wherein the p-doped trench S/D region and the shared bottom p-doped diode region are both composed of a same semiconductor material and a same dopant at a substantially same concentration.
16 . The semiconductor IC device of claim 14 , wherein a top surface of the shared bottom p-doped diode region is below a bottom surface of the p-doped trench S/D region.
17 . The semiconductor IC device of claim 14 , wherein a bottom surface of the first p-doped S/D region, a bottom surface of the second p-doped S/D region, a bottom surface of the first n-doped diode region, and a bottom surface of the second n-doped diode region are substantially coplanar.
18 . The semiconductor IC device of claim 14 , wherein the diode region further comprises:
an inactive region between to the first vertical diode and the second vertical diode, the inactive region comprising:
one or more inactive channels between the first n-doped diode region and the second n-doped diode region; and
an inactive gate around the one or more inactive channels.
19 . The semiconductor IC device of claim 14 , wherein a dopant concentration within the first p-doped S/D region and within the second p-doped S/D region is less than a dopant concentration within the first p-doped trench S/D region.