IP Library Granted Patent US 12,450,006
Granted Patent B2
US 12,450,006 · App. 18/532,980 · Granted Oct 21, 2025

Data storage device, system and controller

Inventors: Jung Min Choi (Icheon-si, KR); Hyun Chul Kim (Icheon-si, KR)
Assignee: SK HYNIX INC.
G06F3/0658G06F3/0619G06F3/0671
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Quick Facts
Patent No.
US 12,450,006
App. No.
18/532,980
Granted
Oct 21, 2025
Kind
B2
Abstract

In an embodiment of the disclosed technology, a defective memory region is detected on the basis of operation information of a memory region included in a memory system and allocated to a host device, a warning signal is transmitted to a host device to which the defective memory region is allocated, and the defective memory region is excluded from a pool of allocatable memory regions to reduce or prevent data loss of a host device using memory regions of the memory system that may occur due to the defective memory region.

Claims (30)

1. A memory system comprising:

a plurality of memory devices, each memory device including a plurality of memory regions configured to store data;

at least one memory controller in communication with the plurality of memory devices and a plurality of host devices and configured to control an operation of each of the plurality of memory devices in response to requests for memory operations from the plurality of host devices; and

a memory management module configured be in communication with at least one of the plurality of memory devices, the plurality of host devices, or the at least one memory controller, and configured to allocate, in response to an allocation request from one or more host devices of the plurality of host devices, one or more memory regions of the plurality of memory regions of one or more memory devices of the plurality of memory devices to the one or more host devices; and transmit, upon identifying a memory region allocated to a first host device of the one or more host devices as a defective memory region with the memory device where an error is predicted to occur, a warning signal to the first host device, and

wherein the memory management module receives a number of error corrections performed by the at least one memory controller, and identifies the defective memory region based on the number of error corrections.

2. The memory system according to claim 1 , wherein the memory management module obtains, from the at least one memory controller, operation information for controlling each of the plurality of memory devices, and identifies the defective memory region based on the operation information.

3. The memory system according to claim 2 , wherein, during a read operation on the plurality of memory regions, the memory management module identifies a memory region as the defective memory region upon performing a number of error corrections by the at least one memory controller such that the number of error corrections is equal to or greater than a preset threshold value.

4. The memory system according to claim 2 , wherein, during a read operation on the plurality of memory regions, the memory management module identifies a memory region adjacent to a known defective memory region as the defective memory region upon performing a number of error corrections by the at least one memory controller such that the number of error corrections is equal to or greater than a preset reference value.

5. The memory system according to claim 2 , wherein the memory management module periodically receives the operation information from the at least one memory controller.

6. The memory system according to claim 2 , wherein the memory management module receives the operation information in response to an interrupt request generated by the at least one memory controller.

7. The memory system according to claim 2 , wherein the memory management module transmits an operation information request command to the at least one memory controller, and receives the operation information.

8. The memory system according to claim 1 , wherein the memory management module identifies the defective memory region by receiving, from the at least one memory controller, information on the defective memory region detected by the at least one memory controller.

9. The memory system according to claim 1 , wherein the memory management module deallocates the defective memory region according to a deallocation request of the first host device which has received the warning signal.

10. The memory system according to claim 1 , wherein the memory management module reallocates, according to a migration request of the first host device which has received the warning signal, a new memory region of the plurality of memory regions to the first host device, and migrates data stored in the defective memory region to the new memory region.

11. The memory system according to claim 1 , wherein the memory management module migrates, according to a migration request of the first host device which has received the warning signal, data stored in the defective memory region to a local memory that is adjacent to the first host device.

12. The memory system according to claim 1 , wherein the memory management module is configured to cause migration of data stored in the defective memory region to a new memory region of the plurality of memory regions, to reallocate the new memory region to the first host device, and transmits allocation information of the reallocated new memory region to the first host device.

13. The memory system according to claim 1 , wherein the memory management module reallocates, upon receiving a new allocation request of the first host device, a memory region of the plurality of memory regions that is different from the defective memory region, as a memory region corresponding to the first host device.

14. The memory system according to claim 1 , wherein the memory management module allocates, in response to an allocation request of a second host device of the plurality of host devices that is different from the first host device, a memory region of the plurality of memory regions that is different from the defective memory region, as a memory region corresponding to the second host device.

15. The memory system according to claim 1 , wherein the memory management module identifies the first host device of the plurality of host devices as being allocated with the defective memory region, based on occupation information from an auxiliary memory configured to store the occupation information regarding the plurality of memory regions allocated to the plurality of host devices.

16. The memory system according to claim 1 , wherein the memory management module stores information on the defective memory region in an auxiliary memory.

17. The memory system according to claim 1 , wherein the memory management module further transmits the warning signal to host devices other than the first host device.

18. The memory system according to claim 1 , wherein the memory management module transmits, to the first host device, the warning signal including at least one of an error level and an error type of an error in the defective memory region.

19. A data storage system comprising:

a plurality of storage devices including a plurality of memory devices each memory device including a plurality of memory regions configured to store data; and

a memory management device located outside the plurality of storage devices, and configured to: allocate one or more memory regions of the plurality of memory regions in response to an allocation request from one or more host devices of a plurality of host devices; and transmit, upon identifying a defective memory region where an error is predicted to occur, a warning signal to a first host device of the plurality of host devices that is allocated with the defective memory region, and

wherein the memory management device receives a number of error corrections performed by the plurality of storage devices, and identifies the defective memory region based on the number of error corrections.

20. A control unit comprising:

at least one memory controller configured to control an operation of a plurality of memory devices, each memory device including a plurality of memory regions configured to store data; and

a memory management module configured to: allocate, in response to an allocation request from one or more host devices of a plurality of host devices, one or more memory regions of the plurality of memory regions to the one or more host devices; and transmit, upon identifying a memory region allocated to a first host device of the one or more host devices as a defective memory region where an error is predicted to occur, a warning signal to a host device of the plurality of host devices that is allocated with the defective memory region, and

wherein the memory management module receives a number of error corrections performed by the at least one memory controller, and identifies the defective memory region based on the number of error corrections.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2023
From: CHOI, JUNG MIN; KIM, HYUN CHUL
To: SK HYNIX INC.
Reel/Frame 065804/0546 →
Priority Claims (1)
KR 10-2023-0089489 · Jul 11, 2023 · national
Continuity (1)
Related Publication 20250021264A1 · Jan 16, 2025
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