IP Library › Granted Patent US 12,712,113
Granted Patent B2
US 12,712,113 · App. 18/542,182 · Granted Aug 18, 2026

Spiral inductors, transformers and baluns formed from flexible dielectric sheets

Inventor: Osman Ersed Akcasu (San Diego, CA)
Assignee: nanoHenry, Inc.
H01F27/2804H01F27/29H01F41/041H01G4/005H01G4/232H01G4/236H01G4/33H10D1/20H10D1/692H01G4/1245
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,712,113
App. No.
18/542,182
Granted
Aug 18, 2026
Kind
B2
Abstract

New types of circuit elements for integrated circuits include structures wherein a thickness dimension is much greater than a width dimension and is more closely spaced than the width dimension in order to attain a tight coupling condition. The structure is suitable to form inductors, capacitors, transmission lines and low impedance power distribution networks in integrated circuits. The width dimension is on the same order of magnitude as skin depth. Embodiments include a spiral winding disposed in a silicon substrate formed of a deep, narrow, conductor-covered spiral ridge separated by a narrow spiral trench. Other embodiments include a wide, thin conductor formed in or on a flexible insulative ribbon and wound with turns adjacent one another, or a conductor in or on a flexible insulative sheet folded into layers with windings adjacent one another Further, a method of manufacture includes directional etching of the deep, narrow spiral trench to form a winding in silicon.

Claims (24)

1 . An inductor comprising:

a conductive element on a flexible dielectric sheet, with a thickness of the conductive element being substantially greater than a width of the conductive element;

a winding of the flexible dielectric sheet formed in a continuous symmetric pattern and wound into a roll so that segments of the conductive element are adjacent one another and separated by the flexible dielectric sheet to attain a tight coupling condition defined as a high coupling coefficient across multiple turns; and

terminals coupled to each end of the conductive element for external electrical connection, wherein the conductive element and the flexible dielectric sheet are folded such that the thickness of portions of the conductive element adjacent to the terminals extends perpendicular to the thickness of at least a portion the conductive element in the roll.

2 . The inductor of claim 1 wherein the width is selected to be on a same order of magnitude as skin depth.

3 . The inductor of claim 1 wherein the winding has a straight innermost segment with a Q that is greater than one at a design frequency of the inductor.

4 . An inductor comprising:

a conductive element on a flexible dielectric ribbon, with a thickness of the conductive element being substantially greater than a width of the conductive element;

a winding disposed in a coil of the flexible dielectric ribbon around a central axis such that the conductive element defines turns adjacent one another and separated by the flexible dielectric ribbon to attain a tight coupling condition defined as a high coupling coefficient across multiple turns; and

terminals coupled to each end of the conductive element for external electrical connection; wherein the conductive element and the flexible dielectric ribbon are folded such that the thickness of portions of the conductive element adjacent to the terminals extends perpendicular to the thickness of at least a portion of the conductive element in the coil.

5 . The inductor of claim 4 wherein the width is selected to be on a same order of magnitude as skin depth.

6 . The inductor of claim 4 wherein the winding has a straight innermost segment with a Q that is greater than one at a design frequency of the inductor.

7 . An electrical component comprising:

a flexible dielectric sheet having first conductive traces disposed thereon, wherein a thickness of the first conductive traces is substantially greater than a width of the first conductive traces, the first conductive traces each having segments forming a continuous symmetric pattern, wherein the flexible dielectric sheet is wound into a roll and arranged so that the segments of the first conductive traces are adjacent one another and separated by the flexible dielectric sheet to attain a tight coupling condition defined as a high coupling coefficient across multiple turns of the roll; and

terminals coupled to each end of the first conductive traces for external electrical connection, wherein the first conductive traces and the flexible dielectric sheet are folded such that the thickness of portions of the first conductive traces adjacent to the terminals extend perpendicular to the thickness of at least a portion of the first conductive traces in the roll.

8 . The electrical component of claim 7 wherein the first conductive traces comprise at least three first conductive traces each having first portions that are substantially a same thickness and second portions that are a different thickness, and wherein each of the first conductive traces are electrically coupled to different pins of the terminals.

9 . The electrical component of claim 7 wherein the flexible dielectric sheet is folded in overlay so that the segments of the first conductive traces are adjacent one another to provide an inductor.

10 . The electrical component of claim 7 wherein the flexible dielectric sheet has one or more second conductive traces disposed thereon, the one or more second conductive traces having a shorter length than the first conductive traces, the first conductive traces forming a primary winding of a transformer and the one or more second conductive traces forming a secondary winding of a transformer.

11 . The electrical component of claim 7 wherein the flexible dielectric sheet has one or more second conductive traces disposed thereon, the one or more second conductive traces having a shorter length than the first conductive traces, the first conductive traces forming a primary winding of a balun and the one or more second conductive traces forming a secondary winding of a balun.

12 . The electrical component of claim 7 wherein the flexible dielectric sheet is a flexible printed circuit board (PCB).

13 . The electrical component of claim 7 wherein a length of the first conductive traces on the flexible dielectric sheet is at least five times longer than a length of one of the terminals.

14 . The electrical component of claim 7 wherein an inner dimension of the multiple turns of the first conductive traces is equal to or greater than a thickness of the first conductive traces.

15 . The electrical component of claim 7 wherein the multiple turns of the first conductive traces include at least five turns.

16 . A printed circuit board (PCB) having the electrical component of claim 7 coupled thereto, wherein the multiple turns of the first conductive traces are disposed on a front side of the PCB, and portions of the flexible dielectric sheet extend through the PCB so that the terminals are electrically coupled to a back side of the PCB.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2026
From: AKCASU, OSMAN ERSED
To: LONESTAR INVENTIONS, L.P.
Reel/Frame 074842/0759 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2026
From: LONESTAR INVENTIONS, L.P.
To: AKCASU, OSMAN ERSED
Reel/Frame 074842/0802 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2026
From: AKCASU, OSMAN ERSED
To: NANOHENRY, INC.
Reel/Frame 074842/0848 →
Continuity (3)
Continuation 17978783 · Nov 1, 2022
Division 15285310 · Oct 4, 2016
Related Publication 20240242874A1 · Jul 18, 2024
References Cited (81)
US 2856577A · Schmidt, Jr. · 1958 [cited by examiner]
US 3068433A · Wroblewski · 1962 [cited by examiner]
US 5519582A · Matsuzaki · 1996 [cited by applicant]
US 5633785A · Parker et al. · 1997 [cited by applicant]
US 6114937A · Burghartz et al. · 2000 [cited by applicant]
US 6982477B2 · Adan · 2006 [cited by applicant]
US 7176773B2 · Shoji · 2007 [cited by applicant]
US 7579553B2 · Moriizumi · 2009 [cited by applicant]
US 8212155B1 · Wright et al. · 2012 [cited by applicant]
US 8749337B2 · Baram et al. · 2014 [cited by applicant]
US 11501908B2 · Akcasu · 2022 [cited by applicant]
US 20020064923A1 · Yamauchi et al. · 2002 [cited by applicant]
US 20040056749A1 · Kahlmann · 2004 [cited by examiner]
US 20040217440A1 · Ng et al. · 2004 [cited by applicant]
US 20050275497A1 · Ramadan et al. · 2005 [cited by applicant]
US 20120068301A1 · Sin · 2012 [cited by examiner]
US 20130293337A1 · Lo · 2013 [cited by examiner]
US 20130321094A1 · Sumida · 2013 [cited by examiner]
US 20140145334A1 · Boyd et al. · 2014 [cited by applicant]
US 20150270237A1 · Chi et al. · 2015 [cited by applicant]
US 20160035477A1 · Yeh · 2016 [cited by examiner]
US 20160064354A1 · Chadda et al. · 2016 [cited by applicant]
US 20160163451A1 · Wang · 2016 [cited by applicant]
US 20160276269A1 · Peng et al. · 2016 [cited by applicant]
US 20170330930A1 · Cook et al. · 2017 [cited by applicant]
US 20180096777A1 · Akcasu · 2018 [cited by applicant]
CN 101449362A · 2009 [cited by applicant]
CN 103855158A · 2014 [cited by applicant]
CN 205104335U · 2016 [cited by applicant]
JP 09145386A · 1997 [cited by applicant]
JP 2005217419A · 2005 [cited by applicant]
JP 2014522561A · 2014 [cited by applicant]
WO 2018067594A1 · 2018 [cited by applicant]
U.S. Appl. No. 15/285,310, Advisory Action, Mailed On Jun. 24, 2020, 3 pages. [cited by applicant]
U.S. Appl. No. 15/285,310, Final Office Action, Mailed On Mar. 3, 2020, 10 pages. [cited by applicant]
U.S. Appl. No. 15/285,310, Final Office Action, Mailed On Nov. 27, 2020, 18 pages. [cited by applicant]
U.S. Appl. No. 15/285,310, Non-Final Office Action, Mailed On Aug. 21, 2019, 13 pages. [cited by applicant]
U.S. Appl. No. 15/285,310, Non-Final Office Action, Mailed On Aug. 5, 2020, 16 pages. [cited by applicant]
U.S. Appl. No. 15/285,310, Non-Final Office Action, Mailed on Sep. 29, 2021, 30 pages. [cited by applicant]
U.S. Appl. No. 15/285,310, Notice of Allowance, Mailed on Jul. 13, 2022, 8 pages. [cited by applicant]
U.S. Appl. No. 17/978,783, Non-Final Office Action, Mailed on Jun. 2, 2023, 13 pages. [cited by applicant]
U.S. Appl. No. 17/978,783, Notice of Allowance, Mailed on Sep. 14, 2023, 10 pages. [cited by applicant]
Ahn et al., “A 50-MHz Fully Integrated Low-Swing Buck Converter Using Packaging Inductors”, IEEE Transaction on Power Electronics, vol. 27, No. 10, Oct. 2012, pp. 4347-4356. [cited by applicant]
Akcasu , “PG-PLANE”, The Three-Dimensional Inductance Simulator for Ground Bounce and Simultaneous Switching Noise for Complex Package Power and Ground Plane Structures, IEEE IEPS, Austin, TX, 1992. [cited by applicant]
Akcasu et al., “Net-An” a Full Three-Dimensional Parasitic Interconnect Distributed RLC Extractor for Large Full Chip Applications, IEEE IEDM 1995, Washington D.C., 1995, pp. 495-498. [cited by applicant]
Akcasu , “Net-An” a full 3D Parasitic Interconnect Distributed RLC Extractor for Large Full Chip Applications, Invited, FSA Modeling Workshop, San Jose, CA, Nov. 8, 1996, 4 pages. [cited by applicant]
Akcasu , “60nm and 90nm Interconnect Modeling Challenges”, Invited, FSA Technical Conference, Oct. 4-7, 2004, 73 pages. [cited by applicant]
Akcasu et al., “A General and Comparative Study of RC(0), RC, RCL and RCLK Modeling of Interconnects and their Impact on the Design of Multi-Giga Hertz Processors”, Invited, IEEE Isqed 2002, Santa Clara, CA, Mar. 2002, … [cited by applicant]
Akcasu et al., “A Practical Approach to Preventing Simultaneous Switching Noise and Ground Bounce Problems in IO Rings”, DesignCon 2003, Jan. 27-30, 2003, 7 pages. [cited by applicant]
Akcasu , “Case Study of On-Chip Inductance Effects (Extraction and Analysis)”, SEMATECH Technical Report, 1998. [cited by applicant]
Akcasu , “Case Study of On-Chip Inductance Effects (Extraction and Analysis)”, Invited, FSA Modeling Workshop, San Jose, CA, May 24, 1999. [cited by applicant]
Akcasu , “Complete Three-Dimensional Simulation of RF IC Blocks for Synthesis, Design and Optimization”, Invited, 12th Annual International Interconnect Technology Conference Short Course IITC 2009, Sapporo, Hokkaido, J… [cited by applicant]
Akcasu et al., “Impact of the On-Chip Inductive Effects on the Power Distribution Networks for Simultaneous Switching Noise and Ground Bounce Analysis for High Speed Processor Design”, Invited, IMAPS Next Generation IC … [cited by applicant]
Akcasu , “Interconnect Parasitic RLC and Delay Variability Below 90nm, Physical Origins and its Impact on the Feature Geometry Scaling”, Invited, IDV 2007, Bangalore, India, Dec. 13-14, 2007, 1 page. [cited by applicant]
Akcasu , “OEA International, Inc. Parasitic Inductance Impact Study Final Report”, SEMATECH, Dec. 27, 1999, 43 pages. [cited by applicant]
Akcasu et al., “SPIRAL and RF-PASS Three Dimensional Design and Analysis Tools for RF Integrated Circuits”, Invited, FSA Workshop, Sep. 8, 2002. [cited by applicant]
Akcasu , “Very Large Scale 3-D Modeling of Interconnect Structures for VLSI Applications”, Invited, 1996 ST CAD, Taiwan, May 1996, pp. 4.2.1-4.2.16. [cited by applicant]
Application No. BR112019006928-3 , Office Action, Mailed On Jul. 19, 2022, 4 pages. [cited by applicant]
Burton et al., “FIVR-Fully Integrated Voltage Regulators on 4th Generation Intel Core SoCs”, Advanced Power Electronics Conference, Fort Worth, TX, Mar. 2014, 8 pages. [cited by applicant]
Cho et al., “Impact of Copper Through-Package Vias on Thermal Performance of Glass Interposers”, IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 5, No. 8, Aug. 2015, pp. 1075-1084. [cited by applicant]
Application No. CN201780074950.0 , Office Action, Mailed On Jun. 23, 2021, 7 pages. [cited by applicant]
Application No. CN201780074950.0 , Office Action, Mailed On Nov. 3, 2020, 8 pages. [cited by applicant]
Application No. EP17859039.4 , Extended European Search Report, Mailed On May 15, 2020, 7 pages. [cited by applicant]
Application No. EP17859039.4 , Notice of Decision to Grant, Mailed On Dec. 16, 2021, 2 pages. [cited by applicant]
IN 201917017400 , “First Examination Report”, Feb. 2, 2021, 7 pages. [cited by applicant]
Application No. JP2019-539730 , Notice of Allowance, Mailed On Feb. 25, 2022, 3 pages. [cited by applicant]
Application No. JP2019-539730 , Office Action, Mailed On Aug. 12, 2021, 8 pages. [cited by applicant]
Application No. KR10-2019-7012946 , Notice of Decision to Grant, Mailed On Dec. 15, 2022, 7 pages. [cited by applicant]
Application No. KR10-2019-7012946 , Office Action, Mailed On Mar. 2, 2022, 10 pages. [cited by applicant]
Kumar et al., “Ultra-High I/O Density Glass/Silicon Interposers for High Bandwidth Smart Mobile Applications”, 2011 Electronic Components and Technology Conference, 2011, pp. 217-223. [cited by applicant]
Kurd et al., “Haswell: A Family of IA 22nm Processors”, ISSCC 2014, San Francisco, CA, Nov. 2014, pp. 112-114. [cited by applicant]
Lai et al., “300mm Size Ultra-thin Glass Interposer Technology and High-Q Embeded Helical Inductor for Mobile Application”, International Electron Device Meeting, Dec. 2013, pp. 13.4.1-13.4.4. [cited by applicant]
Lambert et al., “Package Embedded Inductors for Integrated Voltage Regulators”, 2014, pp. 528-534. [cited by applicant]
Application No. PCT/US2017/054976 , International Preliminary Report on Patentability, Mailed On Apr. 18, 2019, 10 pages. [cited by applicant]
Application No. PCT/US2017/054976 , International Search Report and Written Opinion, Mailed On Mar. 12, 2018, 13 pages. [cited by applicant]
PCT/US2017/054976 , “Invitation to Pay Additional Fees and Partial Search Report”, Jan. 8, 2018, 2 pages. [cited by applicant]
Application No. PID201903542 , Office Action, Mailed On Jun. 16, 2023, 4 pages. [cited by applicant]
Rojas-Gonzales et al., “Design of a Fully-Integrated Buck Voltage Regulator Using Standard CMOS Technology”, 2012, 4 pages. [cited by applicant]
Sturcken et al., “A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI”, IEEE Journal of Solid-State Circuits, vol. 47, No. 8, Aug. 2012, pp. 1935-1945. [cited by applicant]
Sukumaran et al., “Design, Fabrication, and Characterization of Ultrathin 3-D Glass Interposers With Through-Package-Vias at Same Pitch as TSVs in Silicon”, IEEE Transactions on Components, Packaging and Manufacturing T… [cited by applicant]
Yarman et al., “Performance Assessment of Active and Passive Components Manufactured Employing 0.18 micron Silicon CMOS Processing Technology up to 22GHz”, IEEJ International Workshop on AVLSI 2008, Istanbul, Turkey, 20… [cited by applicant]