Image sensor including peak hold circuit
A pixel circuit includes: a photodiode configured to operate in a photovoltaic mode and to accumulate charges corresponding to an incident light amount; a reset transistor configured to reset the accumulated charges of the photodiode; and a peak hold circuit configured to hold an output corresponding to the accumulated charges of the photodiode, the peak hold circuit including a peak hold transistor connected to an output end of the photodiode, a switching transistor configured to turn on/off an output of the peak hold transistor, and a holding capacitor configured to hold an output of the switching transistor. The peak hold transistor operates in a state where no carrier charge or only one carrier charge is present on a channel.
1. A pixel circuit, comprising:
a photodiode configured to operate in a photovoltaic mode and to accumulate charges corresponding to an incident light amount;
a reset transistor configured to reset the accumulated charges of the photodiode; and
a peak hold circuit configured to hold an output corresponding to the accumulated charges of the photodiode, the peak hold circuit including a peak hold transistor connected to an output end of the photodiode, a switching transistor configured to turn on/off an output of the peak hold transistor, and a holding capacitor configured to hold an output of the switching transistor, wherein
the peak hold transistor operates in a state where no carrier charge or only one carrier charge is present on a channel of the peak hold transistor, and wherein
the peak hold transistor operates under a condition that a drain current is less than or equal to kT*μe/L 2 while no charge or only a single charge is present on the channel of the peak hold transistor, where k is a Boltzmann constant, T is an absolute temperature, μe is mobility of an electron, and L is a gate length of the peak hold transistor.
2. The pixel circuit according to claim 1 , wherein
the peak hold transistor is a p-channel transistor, and includes a drain connected to a voltage control transistor, and
injection of charges is controlled by adjusting a drain voltage of the peak hold transistor.
3. The pixel circuit according to claim 1 , wherein
the peak hold transistor is a p-channel transistor, and includes a source connected to a voltage control transistor, and
injection of charges is controlled by adjusting a source voltage of the peak hold transistor.
4. The pixel circuit according to claim 2 , wherein
the voltage control transistor includes one end connected to an injection power supply supplying charges for resetting the holding capacitor, and another end connected to the drain of the peak hold transistor, and
charges from the injection power supply are supplied to the holding capacitor through the voltage control transistor and the peak hold transistor.
5. The pixel circuit according to claim 3 , wherein
the voltage control transistor includes one end connected to a predetermined negative power supply, and another end connected to the source of the peak hold transistor, and
the peak hold transistor is source-follower driven to supply charges from the gate of the peak hold transistor to the holding capacitor.
6. An image sensor, comprising:
a plurality of pixels;
a plurality of analog-to-digital converters; and
a horizontal scan circuit, wherein
each of the pixels includes a photodiode configured to operate in a photovoltaic mode and to accumulate charges corresponding to an incident light amount, a reset transistor configured to reset the accumulated charges of the photodiode, and a peak hold circuit configured to hold an output corresponding to the accumulated charges of the photodiode, wherein the peak hold circuit including a peak hold transistor connected to an output end of the photodiode, a switching transistor configured to turn on/off an output of the peak hold transistor, and a holding capacitor configured to hold an output of the switching transistor, and a source follower circuit configured to output a voltage held in the holding capacitor of the peak hold circuit as a signal voltage,
the peak hold transistor operates under a condition that a drain current is less than or equal to kT*μe/L 2 while no charge or only a single charge is present on a channel of the peak hold transistor, where k is a Boltzmann constant, T is an absolute temperature, μe is mobility of an electron, and L is a gate length of the peak hold transistor,
the analog-to-digital converter converts the signal voltages output from the source-follower circuits of the plurality of pixels into digital signals, and
the horizontal scan circuit serially outputs the digital signals.
7. A pixel circuit, comprising:
a photodiode configured to operate in a photovoltaic mode and to accumulate charges corresponding to an incident light amount;
a reset transistor configured to reset the accumulated charges of the photodiode; and
a peak hold circuit configured to hold an output corresponding to the accumulated charges of the photodiode, the peak hold circuit including a peak hold transistor connected to an output end of the photodiode, a switching transistor configured to turn on/off an output of the peak hold transistor, and a holding capacitor configured to hold an output of the switching transistor, wherein
the peak hold transistor operates in a state where no carrier charge or only one carrier charge is present on a channel of the peak hold transistor, and wherein
the peak hold transistor is a p-channel transistor, and includes a drain connected to a voltage control transistor, and injection of charges is controlled by adjusting a drain voltage of the peak hold transistor, and wherein
the voltage control transistor includes one end connected to an injection power supply supplying charges for resetting the holding capacitor, and another end connected to the drain of the peak hold transistor, and charges from the injection power supply are supplied to the holding capacitor through the voltage control transistor and the peak hold transistor.