IP Library › Granted Patent US 12,363,455
Granted Patent B2
US 12,363,455 · App. 18/393,069 · Granted Jul 15, 2025

Image sensor operating in a photovoltaic mode

Inventors: Yoshiyuki Matsunaga (Kyoto, JP); Keiji Mabuchi (Cupertino, CA); Lindsay Grant (Campbell, CA)
Assignee: OmniVision Technologies, Inc.
H04N25/60H04N25/77H04N25/79H10F39/809H04N25/78
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,363,455
App. No.
18/393,069
Granted
Jul 15, 2025
Kind
B2
Abstract

An image sensor includes a sensor substrate and a circuit substrate. The sensor substrate includes a plurality of sensor substrate-side pixels. Each of the sensor substrate-side pixels includes a photodiode configured to operate in a photovoltaic mode, a reset transistor configured to reset the photodiode, and a pixel source follower transistor connected to an output of the photodiode. The circuit substrate includes circuit substrate-side pixels corresponding to the respective sensor substrate-side pixels of the sensor substrate. Each of the circuit substrate-side pixels includes a peak hold circuit configured to hold a peak of an output of the pixel source follower transistor by receiving the output of the pixel source follower transistor, and a readout source follower transistor configured to read out a voltage held in a holding capacitor. The sensor substrate-side pixels and the respective corresponding circuit substrate-side pixels are connected to each other.

Claims (26)

1. An image sensor, comprising:

a sensor substrate; and

a circuit substrate, wherein

the sensor substrate includes a plurality of sensor substrate-side pixels,

each of the sensor substrate-side pixels includes a photodiode configured to operate in a photovoltaic mode, a reset transistor configured to reset the photodiode, and a pixel source follower transistor connected to an output of the photodiode,

the circuit substrate includes circuit substrate-side pixels corresponding to the respective sensor substrate-side pixels of the sensor substrate,

each of the circuit substrate-side pixels includes a peak hold circuit configured to hold a peak of an output of the pixel source follower transistor by receiving the output of the pixel source follower transistor, and a readout source follower transistor configured to read out a voltage held in a holding capacitor,

the peak hold circuit includes a peak hold transistor configured to allow a current corresponding to the output of the pixel source follower transistor to flow therethrough, a switch transistor configured to turn on/off an output of the peak hold transistor, and the holding capacitor configured to hold an output of the switch transistor, and

the sensor substrate-side pixels and the respective corresponding circuit substrate-side pixels are connected to each other.

2. The image sensor according to claim 1 , wherein a line on a side of the sensor substrate from a source of the pixel source follower transistor is connected to a gate of the peak hold transistor on a side of the circuit substrate through a pixel contact.

3. The image sensor according to claim 2 , wherein a protective transistor is connected to a line connecting the pixel contact on the circuit substrate and a gate of the peak hold transistor.

4. The image sensor according to claim 1 , wherein

the pixel source follower transistor performs source follower operation in a state where number of carrier charges on a channel of the pixel source follower transistor is one or zero, and

a current in the source follower operation is greater than Idrk 2 /Ideq, where Idrk is a dark current in the pixel source follower transistor, and Ideq is an equivalent dark current converted at an output end of a photodiode.

5. The image sensor according to claim 1 , further comprising:

a vertical scan circuit configured to drive the sensor substrate-side pixels on the sensor substrate and the circuit substrate-side pixels on the circuit substrate;

an analog-to-digital converter configured to convert an analog signal output from each of the sensor substrate-side pixels into a digital signal; and

a horizontal scan circuit configured to serially output the digital signals obtained by the analog-to-digital converter.

6. The image sensor according to claim 1 , further comprising:

a vertical scan circuit configured to drive the sensor substrate-side pixels on the sensor substrate and the circuit substrate-side pixels on the circuit substrate;

an analog-to-digital converter configured to convert an analog signal output from each of the circuit substrate-side pixels into a digital signal; and

a horizontal scan circuit configured to serially output the digital signals obtained by the analog-to-digital converter.

7. The image sensor according to claim 1 , wherein

the sensor substrate-side pixels are arranged in a matrix on the sensor substrate,

the circuit substrate-side pixels are arranged in a matrix on the circuit substrate, and

outputs of the readout source follower transistors of the circuit substrate-side pixels in each column are connected to one output line extending in a vertical direction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2024
From: MATSUNAGA, YOSHIYUKI; MABUCHI, KEIJI; GRANT, LINDSAY
To: OMNIVISION TECHNOLOGIES, INC.
Reel/Frame 066002/0717 →
Continuity (1)
Related Publication 20250211871A1 · Jun 26, 2025
References Cited (9)
US 6512544B1 · Merrill · 2003 [cited by examiner]
US 9338381B2 · Kondo · 2016 [cited by applicant]
US 10757350B2 · Tashiro · 2020 [cited by examiner]
US 11196947B2 · Ni · 2021 [cited by applicant]
US 12281937B1 · Matsunaga · 2025 [cited by examiner]
US 20250106533A1 · Matsunaga · 2025 [cited by examiner]
US 20250159372A1 · Matsunaga · 2025 [cited by examiner]
US 20250159373A1 · Matsunaga · 2025 [cited by examiner]
Image Sensor to Supress Flicker; U.S. Appl. No. 18/507,301, filed Nov. 13, 2023; Yoshiyuki Matsunaga, et al. [cited by applicant]