Pixel circuit and driving method thereof, and display device
A pixel circuit and a driving method thereof, and a display device are disclosed. The pixel circuit includes a driving circuit, a data writing circuit, a reset circuit, a light-emitting control circuit and a light-emitting element. The driving circuit includes a control terminal, a first terminal and a second terminal; the data writing circuit is connected to a first node to apply a data voltage; the reset circuit is connected to the first node to apply a reference voltage. The pixel circuit further includes a partition control circuit, which is connected to the first node and the control terminal, and is configured to apply the data voltage and the reference voltage to the control terminal; the reset circuit is connected to one of the first terminal and the second terminal of the driving circuit, and the reset circuit is further configured to apply an initialization voltage to the driving circuit.
1. A pixel circuit, comprising:
a driving circuit, a data writing circuit, a reset circuit, a light-emitting control circuit and a light-emitting element,
wherein the driving circuit comprises a control terminal, a first terminal and a second terminal, and the driving circuit is configured to control a driving current flowing through the first terminal and the second terminal for driving the light-emitting element to emit light;
the light-emitting control circuit is connected to the first terminal of the driving circuit and a first voltage terminal, and is configured to apply a voltage of the first voltage terminal to the first terminal of the driving circuit in response to a light-emitting control signal;
a first terminal of the light-emitting element is configured to receive the driving current, and a second terminal of the light-emitting element is connected to a second voltage terminal;
an input terminal of the data writing circuit is connected to a data line, an output terminal of the data writing circuit is connected to a first node, and the data writing circuit is configured to apply a data voltage to the first node in response to a first control signal;
a first output terminal of the reset circuit is connected to the first node, and the reset circuit is configured to apply a reference voltage to the first node in response to a second control signal;
the pixel circuit further comprises a partition control circuit, the partition control circuit comprises a first terminal and a second terminal, the first terminal of the partition control circuit is connected to the first node, the second terminal of the partition control circuit is connected to the control terminal of the driving circuit, and the partition control circuit is configured to apply at least one of the data voltage and the reference voltage to the control terminal of the driving circuit in response to a partition control signal; and
a second output terminal of the reset circuit is connected to one of the first terminal and the second terminal of the driving circuit, and the reset circuit is further configured to apply an initialization voltage to one terminal, connected to the second output terminal, of the first terminal and the second terminal of the driving circuit in response to the partition control signal and a third control signal.
2. The pixel circuit according to claim 1 , wherein the partition control circuit comprises a partition control transistor, the reset circuit comprises a first reset transistor, and a gate electrode of the partition control transistor and a gate electrode of the first reset transistor are electrically connected to a same partition control signal line to receive the partition control signal.
3. The pixel circuit according to claim 2 , wherein the reset circuit further comprises a second reset transistor, and a gate electrode of the second reset transistor is configured to receive the third control signal.
4. The pixel circuit according to claim 3 , wherein an input terminal of the first reset transistor is connected to a reset signal line, an output terminal of the first reset transistor is connected to a first terminal of the second reset transistor, and a second terminal of the second reset transistor is the second output terminal.
5. The pixel circuit according to claim 2 , wherein the gate electrode of the partition control transistor is connected to the partition control signal line to receive the partition control signal, a first electrode of the partition control transistor is connected to the first node, and a second electrode of the partition control transistor is connected to the control terminal of the driving circuit.
6. The pixel circuit according to claim 1 , wherein the second output terminal of the reset circuit is connected to the first terminal of the driving circuit.
7. The pixel circuit according to claim 1 , further comprising a storage circuit, a first terminal of the storage circuit is connected to a second node, a second terminal of the storage circuit is connected to a third node, the control terminal of the driving circuit is connected to the second node, and the second terminal of the driving circuit is connected to the third node.
8. The pixel circuit according to claim 7 , wherein the light-emitting control circuit comprises a light-emitting control transistor, the driving circuit comprises a driving transistor, a gate electrode of the light-emitting control transistor is connected to a light-emitting control signal line to receive the light-emitting control signal, a first electrode of the light-emitting control transistor is connected to the first voltage terminal, a second electrode of the light-emitting control transistor is connected to a first electrode of the driving transistor, a gate electrode of the driving transistor is connected to the second node, and a second electrode of the driving transistor is connected to the third node.
9. The pixel circuit according to claim 7 , wherein the storage circuit comprises a first capacitor, a first electrode plate of the first capacitor is connected to the second node, and a second electrode plate of the first capacitor is connected to the third node; and
the pixel circuit comprises a second capacitor, a first electrode plate of the second capacitor is connected to the first terminal of the light-emitting element, a second electrode plate of the second capacitor is connected to the second terminal of the light-emitting element, and a capacitance value of the second capacitor is greater than a capacitance value of the first capacitor.
10. The pixel circuit according to claim 1 , further comprising a storage circuit, a first terminal of the storage circuit is connected to a second node, a second terminal of the storage circuit is connected to a third node, the control terminal of the driving circuit is connected to the second node, and the second terminal of the driving circuit is connected to the third node; and
the second output terminal of the reset circuit is connected to the third node.
11. The pixel circuit according to claim 1 , wherein the data writing circuit comprises a data writing transistor, a gate electrode of the data writing transistor is connected to a first control signal line to receive the first control signal, a first electrode of the data writing transistor is connected to the data line to receive a data signal, and a second electrode of the data writing transistor is connected to the first node.
12. The pixel circuit according to claim 1 , wherein the reset circuit comprises a third reset transistor, a gate electrode of the third reset transistor is connected to a second control signal line to receive the second control signal, a first electrode of the third reset transistor is connected to a reset signal line to receive a reference signal, and a second electrode of the third reset transistor is the first output terminal.
13. The pixel circuit according to claim 1 , wherein the first terminal of the light-emitting element is connected to the second terminal of the driving circuit.
14. A display device, comprising a display region and a peripheral region around the display region,
wherein the display device comprises a plurality of sub-pixels in the display region, and at least part of the sub-pixels respectively comprise the pixel circuit according to claim 1 ; and
display device further comprises a plurality of partition control signal lines, the display region comprises a plurality of sub-regions, and partition control circuits of sub-pixels in at least two sub-regions are electrically connected to different partition control signal lines.
15. The display device according to claim 14 , further comprising:
a circuit board in the peripheral region;
a gate driving circuit structure in the peripheral region;
a plurality of data lines arranged along a first direction; and
a plurality of first control signal lines arranged along a second direction, the second direction intersecting with the first direction,
wherein the circuit board is configured to provide partition control signals for the partition control signal lines, the circuit board is further configured to provide data signals for the data lines, and the gate driving circuit structure is configured to provide first control signals for the first control signals.
16. The display device according to claim 15 , wherein the plurality of partition control signal lines comprise a plurality of first partition control signal lines and a plurality of second partition control signal lines, at least one of the plurality of first partition control signal lines extends along the first direction, at least one of the plurality of second partition control signal lines extends along the second direction, and one first partition control signal line is electrically connected to the circuit board through at least one second partition control signal line; and
control terminals of partition control circuits of sub-pixels in a same sub-region are electrically connected to a same first partition control signal line, and are insulated from different first partition control signal lines electrically connected to sub-pixels in different sub-regions.
17. The display device according to claim 15 , wherein the second output terminal of the reset circuit is connected to the first terminal of the driving circuit.
18. The display device according to claim 17 , wherein the partition control circuit comprises a partition control transistor, the reset circuit comprises a first reset transistor, and in a same sub-pixel, a gate electrode of the partition control transistor and a gate electrode of the first reset transistor is electrically connected to a same partition control signal line to receive the partition control signal; and
at least two sub-pixels share a same first reset transistor.
19. The display device according to claim 17 , wherein at least two sub-pixels share a same light-emitting control circuit.
20. A driving method for the pixel circuit according to claim 1 , comprising a reset phase, a compensation phase, a data writing phase and a light-emitting phase,
wherein in the reset phase, inputting the second control signal, the partition control signal and the third control signal to turn on the reset circuit and the partition control circuit, to reset the control terminal of the driving circuit and reset one terminal, connected to the second output terminal of the reset circuit, of the first terminal and the second terminal of the driving circuit;
in the compensation phase, inputting the second control signal, the light-emitting control signal and the partition control signal to keep turning on the reset circuit, the partition control circuit and the driving circuit and turn on the light-emitting control circuit, to compensate the second terminal of the driving circuit through a voltage of the first voltage terminal;
in the data writing phase, inputting the first control signal and the partition control signal, to keep turning on the partition control circuit and turn on the data writing circuit, to apply the data voltage to the control terminal of the driving circuit; and
in the light-emitting phase, inputting the light-emitting control signal and the partition control signal, to keep turning on the partition control circuit and turn on the light-emitting control circuit and the driving circuit, to generate a driving current, and drive the light-emitting element to emit light.