Display substrate and method for manufacturing same, and display apparatus

1. A display substrate, comprising:

a substrate and a plurality of sub-pixels disposed on the substrate, wherein:

at least one of the plurality of sub-pixels comprises a pixel drive circuit and a light emitting element electrically connected to the pixel drive circuit; the pixel drive circuit comprises a plurality of transistors and at least one storage capacitor;

in a direction perpendicular to the substrate, the display substrate comprises a semiconductor layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer arranged on the substrate sequentially;

the semiconductor layer comprises active layers of the plurality of transistors;

the first metal layer at least comprises a scan line extending in a first direction, gate electrodes of the plurality of transistors, and a first capacitor plate of the storage capacitor;

the second metal layer at least comprises a scan connection line extending along the first direction, wherein an insulating layer between the second metal layer and the first metal layer is provided with a first via, and the scan connection line is in contact with the scan line exposed through the first via;

the third metal layer at least comprises a second capacitor plate of the storage capacitor;

the fourth metal layer at least comprises a data line extending in a second direction perpendicular to the first direction; source electrodes and drain electrodes of the plurality of transistors;

the scan line comprises a first part and a second part connected in sequence along a first direction, a projection of the first part on the substrate is overlapped with a projection of the fourth metal layer on the substrate, a projection of the second part on the substrate is not overlapped with the projection of the fourth metal layer on the substrate, and an average length of the second part in the second direction is greater than an average length of the first part in the second direction;

the pixel drive circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a storage capacitor;

a gate electrode of the first transistor is connected to a second electrode of the third transistor, the first capacitor plate of the storage capacitor and a second electrode of the fourth transistor, a first electrode of the first transistor is connected to a second electrode of the second transistor, a second electrode of the first transistor is connected to the second capacitor plate of the storage capacitor, a first electrode of the fifth transistor and a first electrode of the light emitting element;

a gate electrode of the second transistor is connected to an emitting control line, and a first electrode of the second transistor is connected to a first power supply line;

a gate electrode of the third transistor is connected to a first control signal line, and a first electrode of the third transistor is connected to a reference voltage line;

a gate electrode of the fourth transistor is connected to the scan line, and a first electrode of the fourth transistor is connected to the data line; and

a gate electrode of the fifth transistor is connected to a second control signal line, and a second electrode of the fifth transistor is connected to an initial voltage line;

the third transistor, the fourth transistor, and the fifth transistor are double gate transistors; each double gate transistor comprises two gate electrodes connected to each other; and

the first capacitor plate of the storage capacitor and the gate electrode of the first transistor are integrally structured.

2. The display substrate of claim 1 , wherein the first part has a first edge and a second edge extending in a first direction, the second part has a first edge and a third edge extending in a first direction, the second edge and the third edge are located on a same side of the first edge along the second direction, and the third edge is located on a side of the second edge away from the first edge.

3. The display substrate of claim 2 , wherein the first edge is an upper edge of the first part and the second part, the second edge is a lower edge of the first part, and the third edge is a lower edge of the second part.

4. The display substrate of claim 1 , wherein a projection of the scan connection line on the substrate comprises a projection of the scan line on the substrate.

5. The display substrate of claim 1 , wherein a material of the first metal layer is molybdenum, and the second metal layer comprises a three-layer stacked structure formed of titanium, aluminum, and titanium.

6. The display substrate of claim 1 , wherein the fourth metal layer further comprises a first power supply line extending in a second direction; and six columns of sub-pixels are provided between two adjacent first power supply lines.

7. The display substrate of claim 6 , wherein the first metal layer further comprises a power connection line extending in a first direction, wherein the power connection line is connected to the first power supply line and the six columns of sub-pixels.

8. The display substrate of claim 1 , further comprising a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, wherein

the first insulating layer is arranged between the semiconductor layer and the first metal layer, the second insulating layer is arranged between the first metal layer and the second metal layer, the third insulating layer is arranged between the second metal layer and the third metal layer, and the fourth insulating layer is arranged between the third metal layer and the fourth metal layer.

9. The display substrate of claim 1 , further comprising a fifth metal layer disposed on a side of the fourth metal layer away from the substrate, wherein

the fifth metal layer at least comprises a connection electrode for electrically connecting the pixel drive circuit and the light emitting element.

10. The display substrate of claim 1 , wherein:

the first metal layer further comprises a first control signal line, a second control signal line and an emitting control line;

the third metal layer further comprises a reference voltage line and an initial voltage line; and

the first control signal line, the second control signal line, the emitting control line, the reference voltage line and the initial voltage line all extend along the first direction.

11. The display substrate of claim 10 , wherein:

in the second direction, the first control signal line and the second control signal line are located on both sides of the scan line respectively, and the emitting control line is located on a side of the second control signal line away from the scan line; and

a projection of the reference voltage line on the substrate is located on a side of a projection of the first control signal line on the substrate away from a projection of the scan line on the substrate, and a projection of the initial voltage line on the substrate is located between a projection of the second control signal line and a projection of the emitting control line on the substrate.

12. A display device, comprising the display substrate of claim 1 .

13. A preparation method for a display substrate, wherein:

the display substrate comprises a substrate and a plurality of sub-pixels disposed on the substrate, at least one of the plurality of sub-pixels comprises a pixel drive circuit and a light emitting element electrically connected to the pixel drive circuit; the pixel drive circuit comprises a plurality of transistors and at least one storage capacitor;

the preparation method comprises:

sequentially forming a semiconductor layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer on the substrate; the semiconductor layer comprises active layers of the plurality of transistors; the first metal layer at least comprises a scan line extending in a first direction, gate electrodes of the plurality of transistors, and a first capacitor plate of the storage capacitor; the second metal layer at least comprises a scan connection line extending along the first direction; an insulating layer between the second metal layer and the first metal layer is provided with a first via, and the scan connection line is in contact with the scan lines exposed through the first via; the third metal layer at least comprises a second capacitor plate of the storage capacitor; the fourth metal layer at least comprises a data line extending in a second direction perpendicular to the first direction and a source electrodes and drain electrodes of the plurality of transistors; and

the scan line comprises a first part and a second part connected in sequence along a first direction, a projection of the first part on the substrate is overlapped with a projection of the fourth metal layer on the substrate, a projection of the second part on the substrate is not overlapped with the projection of the fourth metal layer on the substrate, and an average length of the second part in the second direction is greater than an average length of the first part in the second direction;

the pixel drive circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a storage capacitor;

a gate electrode of the first transistor is connected to a second electrode of the third transistor, the first capacitor plate of the storage capacitor and a second electrode of the fourth transistor, a first electrode of the first transistor is connected to a second electrode of the second transistor, a second electrode of the first transistor is connected to the second capacitor plate of the storage capacitor, a first electrode of the fifth transistor and a first electrode of the light emitting element;

a gate electrode of the second transistor is connected to an emitting control line, and a first electrode of the second transistor is connected to a first power supply line;

a gate electrode of the third transistor is connected to a first control signal line, and a first electrode of the third transistor is connected to a reference voltage line;

a gate electrode of the fourth transistor is connected to the scan line, and a first electrode of the fourth transistor is connected to the data line; and

a gate electrode of the fifth transistor is connected to a second control signal line, and a second electrode of the fifth transistor is connected to an initial voltage line;

the third transistor, the fourth transistor, and the fifth transistor are double gate transistors;

each double gate transistor comprises two gate electrodes connected to each other; and

the first capacitor plate of the storage capacitor and the gate electrode of the first transistor are integrally structured.