Circuit device with multiple parallel data paths
An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.
1. A system comprising:
a processing unit;
a first data path configured to couple a source device to a target device, wherein the first data path is a blocking data path and includes:
a first interconnect segment configured to couple to the source device;
a second interconnect segment configured to couple to the target device; and
a bridge circuit coupled between the first interconnect segment and the second interconnect segment;
a data read circuit coupled to the processing unit and configured to couple to the source device;
a data write circuit coupled to the processing unit and configured to couple to the target device; and
a second data path coupled between the data read circuit and the data write circuit, wherein the second data path is a non-blocking data path.
2. The system of claim 1 , wherein:
the data read circuit is configured to couple to the source device via the first interconnect segment; and
the data write circuit is configured to couple to the target device via the second interconnect segment.
3. The system of claim 1 , wherein the second data path includes a streaming interconnect coupled between the data read circuit and the data write circuit.
4. The system of claim 1 , wherein:
the processing unit is configured to cause a transfer of data between the source device and the target device via the data read circuit and the data write circuit by providing a first instruction to the data read circuit; and
the data read circuit is configured to, in response to the first instruction, transmit a second instruction to the data write circuit.
5. The system of claim 4 , wherein the data read circuit is configured to transmit the second instruction to the data write circuit via the second data path.
6. The system of claim 1 , wherein at least one of the source device and the target device includes an analog-to-digital converter or a serial peripheral interconnect interface.
7. The system of claim 1 further comprising the source device and the target device.
8. The system of claim 1 , wherein:
the data read circuit is a first data read circuit;
the data write circuit is a first data write circuit; and
the system further comprises:
a second data write circuit, wherein the second data write circuit and the first data read circuit are coupled to the source device by the first interconnect segment; and
a second data read circuit, wherein the second data read circuit and the first data write circuit are coupled to the target device by the second interconnect segment.
9. The system of claim 1 , wherein the source device and the target device each include a peripheral device or a memory.
10. A system comprising:
a source device;
a target device;
a first data path coupled between the source device and the target device, wherein the first data path is a blocking data path and includes:
a first interconnect segment coupled to the source device;
a second interconnect segment coupled to the target device; and
a bridge circuit coupled between the first interconnect segment and the second interconnect segment;
a read circuit coupled to the source device;
a write circuit coupled to the target device; and
a second data path coupled between the read circuit and the write circuit, wherein the second data path is a non-blocking data path.
11. The system of claim 10 , wherein:
the read circuit is coupled to the source device via the first interconnect segment; and
the write circuit is coupled to the target device via the second interconnect segment.
12. The system of claim 10 , wherein the second data path includes a streaming interconnect coupled between the read circuit and the write circuit.
13. The system of claim 10 , wherein the read circuit is configured to:
receive a first instruction regarding a transfer of data between the source device and the target device via the read circuit and the write circuit;
in response to the first instruction, transmit a second instruction to the write circuit; and
in conjunction with the write circuit, transfer the data between the source device and the target device.
14. The system of claim 10 , wherein the source device and the target device each include a peripheral device or a memory.
15. The system of claim 10 , wherein at least one of the source device and the target device includes an analog-to-digital converter or a serial peripheral interconnect interface.
16. The system of claim 13 , wherein the read circuit is configured to transmit the second instruction to the write circuit via the second data path.
17. The system of claim 10 , wherein:
the read circuit is a first read circuit;
the write circuit is a first write circuit; and
the system further comprises:
a second write circuit, wherein the second write circuit and the first read circuit are coupled to the source device by the first interconnect segment; and
a second read circuit, wherein the second read circuit and the first write circuit are coupled to the target device by the second interconnect segment.
18. A device comprising:
a first data path configured to couple between a source device and a target device, wherein the first data path is a blocking data path and includes:
a first interconnect segment coupled to the source device;
a second interconnect segment coupled to the target device; and
a bridge circuit coupled between the first interconnect segment and the second interconnect segment;
a read circuit configured to couple to the source device;
a write circuit configured to couple to the target device; and
a second data path coupled between the read circuit and the write circuit, wherein the second data path is a non-blocking data path.
19. The device of claim 18 , wherein the second data path includes a streaming interconnect coupled between the read circuit and the write circuit.
20. The device of claim 19 , wherein the read circuit is configured to:
transmit an instruction to the write circuit associated with a transfer of data between the source device and the target device via the read circuit and the write circuit; and
in conjunction with the write circuit, transfer the data between the source device and the target device.