IP Library › Granted Patent US 8,122,164
Granted Patent B2
US 8,122,164 · App. 12/555,090 · Granted Feb 21, 2012

Information processing apparatus having first DMA controller and second DMA controller wherein selection circuit determines which DMA will perform data transfer based on higher data transfer performance

Assignee: Canon Kabushiki Kaisha
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Quick Facts
Patent No.
US 8,122,164
App. No.
12/555,090
Granted
Feb 21, 2012
Kind
B2
Abstract

Provided is an information processing apparatus and method of controlling same in which, when data transfer is performed among a plurality of control circuits, which control circuit is used to execute data transfer is controlled appropriately based on the transfer conditions of data transfer. To accomplish this, the apparatus has first and second control circuits, a request for data transfer performed between the first and second control circuits is acquired, the transfer conditions of the acquired data transfer are analyzed and which of the first and second control circuits is to execute the data transfer is selected.

Claims (18)

1. An information processing apparatus having a first control circuit including a first volatile memory and a first DMA controller, and a second control circuit including a second volatile memory and a second DMA controller, the first and second control circuits each including a storage unit that stores a table in which data transfer performance of each control circuit is defined for a different transfer condition, the first DMA controller and the second DMA controller being capable of respectively executing data transfers in both a first direction from the first volatile memory to the second volatile memory and a second direction from the second volatile memory to the first volatile memory, the apparatus comprising:

an acquisition unit that acquires a request for a data transfer performed between the first volatile memory and second volatile memory;

an analyzing unit that analyzes whether the data transfer should be executed in either the first direction or the second direction, based on the request acquired by the acquisition unit;

a selecting unit that selects one of the first and second DMA controllers having a data transfer rate that is faster than a data transfer rate of another of the first and second DMA controllers, when the data transfer is executed in a direction analyzed by the analyzing unit,

wherein the selecting unit selects, as a DMA controller to execute the data transfer, a DMA controller having a high data transfer performance in accordance with a transfer condition analyzed by the analyzing unit; and

a control unit that exercises control in such a manner that the data transfer is executed by the first control circuit if the first DMA controller is selected by the selecting unit and is executed by the second control circuit if the second DMA controller is selected by the selecting unit.

2. The apparatus according to claim 1 , wherein

the selecting unit selects the first DMA controller in a case where data to be transferred is data that has been stored in the first volatile memory and the first control circuit has a right to access the second volatile memory that is the transfer destination; and

the selecting unit selects the second DMA controller in a case where data to be transferred is data that has been stored in the first volatile memory and the first control circuit does not have the right to access the second volatile memory that is the transfer destination, or in a case where data to be transferred is data that has been stored in the second volatile memory.

3. A method of controlling an information processing apparatus having a first control circuit including a first volatile memory and a first DMA controller, and a second control circuit including a second volatile memory and a second DMA controller, the first and second control circuits each including a storage unit that stores a table in which data transfer performance of each control circuit is defined for a different transfer condition, the first DMA controller and the second DMA controller being capable of respectively executing data transfers in both a first direction from the first volatile memory to the second volatile memory and a second direction from the second volatile memory to the first volatile memory, the method comprising steps of:

acquiring a request for data transfer performed between the first volatile memory and second volatile memory;

analyzing whether a data transfer should be executed in either the first direction or the second direction, based on the request acquired in the acquiring step;

selecting one of the first and second DMA controllers having a data transfer rate that is faster than a data transfer rate of another of the first and second DMA controllers, when the data transfer is executed in a direction analyzed in the analyzing step,

wherein the selecting includes selecting, as a DMA controller to execute the data transfer, a DMA controller having a high data transfer performance in accordance with a transfer condition analyzed by the analyzing unit; and

exercising control in such a manner that data transfer is executed by the first control circuit if the first DMA controller is selected at the selecting step and is executed by the second control circuit if the second DMA controller is selected in the selecting step.

4. The method according to claim 3 , wherein

the first DMA controller is selected in a case where data to be transferred is data that has been stored in the first volatile memory and the first control circuit has a right to access the second volatile memory that is the transfer destination; and

the second DMA controller is selected in a case where data to be transferred is data that has been stored in the first volatile memory and the first control circuit does not have the right to access the second volatile memory that is the transfer destination, or in a case where data to be transferred is data that has been stored in the second volatile memory.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 24, 2009
From: YOKOMIZO, SO
To: CANON KABUSHIKI KAISHA
Reel/Frame 023698/0902 →
Priority Claims (1)
JP 2008-249134 · Sep 26, 2008 · national
Continuity (1)
Related Publication 20100082850A1 · Apr 1, 2010