IP Library › Granted Patent US 12,353,034
Granted Patent B2
US 12,353,034 · App. 18/589,180 · Granted Jul 8, 2025

Optical integrated circuit structure including edge coupling protective features and method of forming same

Inventors: Chen-Hao Huang (Taoyuan, TW); Sui-Ying Hsu (New Taipei, TW); YuehYing Lee (Hsinchu, TW); Chia-Ping Lai (Hsinchu, TW); Chien-Ying Wu (Hsinchu, TW); Hau-Yan Lu (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company Limited
G02B6/4248G02B6/12G02B6/12002G02B6/12004G02B6/136G02B6/4206G02B6/4274H01L23/5226H01L23/53228G02B6/30G02B6/4228G02B6/4236H01L21/30604H01L21/3065H01L21/31116H01L23/585
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Quick Facts
Patent No.
US 12,353,034
App. No.
18/589,180
Granted
Jul 8, 2025
Kind
B2
Abstract

An optical integrated circuit (IC) structure includes: a substrate including a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot; a semiconductor layer disposed on the substrate; a dielectric structure disposed on the semiconductor layer; an interconnect structure disposed in the dielectric structure; a plurality of vents that extend through a coupling region of the dielectric structure and expose the undercut; a fiber cavity that extends through the coupling region of dielectric structure and exposes the fiber slot; and a barrier ring disposed in the dielectric structure, the barrier ring surrounding the interconnect structure and routed around the perimeter of the coupling region.

Claims (49)

1. An optical integrated circuit (IC) structure comprising:

a substrate comprising a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot;

a bottom oxide layer disposed on the substrate;

a semiconductor layer disposed on the bottom oxide layer;

vents that extend through the semiconductor layer and the bottom oxide layer to expose the undercut; and

a barrier layer disposed on surfaces of the vents, the undercut, and the fiber slot.

2. The IC structure of claim 1 , further comprising:

a dielectric structure disposed on the semiconductor layer;

an interconnect structure disposed in the dielectric structure; and

a barrier ring disposed in the dielectric structure and surrounding the interconnect structure.

3. The IC structure of claim 2 , wherein the barrier ring separates the interconnect structure from the vents and the fiber slot, and the barrier ring is configured to prevent contaminants from diffusing into the interconnect structure.

4. The IC structure of claim 2 , wherein:

the barrier ring and the interconnect structure comprise copper or a copper alloy; and

the barrier ring has a thickness of at least 10 microns.

5. The IC structure of claim 2 , further comprising a fiber cavity that extends through the semiconductor layer and the bottom oxide layer to expose the fiber slot.

6. The IC structure of claim 1 , wherein a portion of the semiconductor layer that is disposed over the undercut and extends between the vents is configured to operate as an optical waveguide.

7. The IC structure of claim 1 , wherein the barrier layer comprises a dielectric material.

8. The IC structure of claim 7 , wherein the barrier layer has a thickness of at least 10 microns.

9. An optical integrated circuit (IC) structure comprising:

a substrate comprising a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot;

a semiconductor layer disposed on the substrate;

a dielectric structure disposed on the semiconductor layer;

vents that extend through a coupling region of the dielectric structure and expose the undercut; and

a dielectric material disposed on surfaces of the vents, the undercut, and the fiber slot.

10. The IC structure of claim 9 , wherein the dielectric material has a thickness of at least 50 nanometers.

11. The IC structure of claim 9 , further comprising:

an interconnect structure disposed in the dielectric structure; and

a barrier ring disposed in the dielectric structure and surrounding the interconnect structure.

12. The IC structure of claim 11 , wherein the barrier ring and the interconnect structure comprise copper or a copper alloy.

13. The IC structure of claim 11 , further comprising a fiber cavity that extends through the dielectric structure and exposes the fiber slot.

14. The IC structure of claim 13 , wherein:

the dielectric material is disposed on surfaces of the fiber cavity; and

the barrier ring contacts the dielectric material on opposing sides of the fiber cavity.

15. The IC structure of claim 9 , wherein the substrate comprises an optical waveguide that is disposed over the undercut and that extends between the vents to the fiber slot.

16. An optical integrated circuit (IC) structure comprising:

a substrate comprising a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot;

a semiconductor layer disposed on the substrate and comprising an optical waveguide disposed over the undercut;

inter-metal dielectric (IMD) layers disposed on the semiconductor layer;

vents that extend through the IMD layers and the semiconductor layer to expose the undercut;

an interconnect structure disposed in the IMD layers; and

a barrier ring disposed in the IMD layers and surrounding the interconnect structure.

17. The IC structure of claim 16 , further comprising:

a fiber cavity that extends through the IMD layers and the semiconductor layer to expose the fiber slot; and

a barrier layer disposed on surfaces of the vents, the undercut, the fiber slot, and the fiber cavity.

18. The IC structure of claim 16 , wherein the optical waveguide is disposed between the vents.

19. The IC structure of claim 16 , wherein the barrier ring separates the interconnect structure from the vents and the fiber slot, and the barrier ring is configured to prevent contaminants from diffusing into the interconnect structure.

20. The IC structure of claim 16 , wherein:

the barrier ring and the interconnect structure comprise copper or a copper alloy; and

the barrier ring has a thickness of at least 10 microns.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2024
From: HUANG, CHEN-HAO; LU, HAU-YAN; HSU, SUI-YING; LEE, YUEHYING; WU, CHIEN-YING; LAI, CHIA-PING
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
Reel/Frame 066584/0090 →
Continuity (2)
Continuation 17460789 · Aug 30, 2021
Related Publication 20240201458A1 · Jun 20, 2024
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