Isolation of compartments in a layered printed circuit board, and apparatus and methods for the same
In some embodiments, an apparatus can include a printed circuit board (PCB) that has layers and includes a first portion and a second portion. The first portion can have a data port and a power port. A first layer is associated with data of the first portion of the PCB, and a second layer is associated with power of the first portion of the PCB. The second portion can have a data port and a power port. A third layer is associated with data of the second portion, and a fourth layer is associated with power of the second portion. The first portion or the second portion can have vias defining an electromagnetic interference (EMI) shield. The apparatus can include a power filter and a data filter that can, respectively, isolate power and data of the first portion from the second portion.
1. An apparatus, comprising:
a printed circuit board (PCB) having a plurality of layers and including a first portion and a second portion mutually exclusive from the first portion of the PCB, the PCB includes a third portion mutually exclusive and physically separate from the first portion of the PCB and the second portion of the PCB,
a first layer from the plurality of layers having a first portion and a second portion mutually exclusive and physically separate from the first portion of the first layer, the first portion of the first layer being associated with power of the first portion of the PCB, the second portion of the first layer being a dielectric in the second portion of the PCB,
a second layer from the plurality of layers having a first portion and a second portion mutually exclusive and physically separate from the first portion of the second layer, the first portion of the second layer being a dielectric in the first portion of the PCB, the second portion of the second layer being associated with power of the second portion of the PCB,
a third layer from the plurality of layers being a dielectric in the first portion of the PCB and the second portion of the PCB, the third layer being disposed between the first layer and the second layer,
a fourth layer from the plurality of layers having a first portion, a second portion and a third portion, the first portion of the fourth layer is mutually exclusive and physically separate from the second portion of the fourth layer and the third portion of the fourth layer, the second portion of the fourth layer is mutually exclusive and physically separate from the third portion of the fourth layer,
the first portion of the fourth layer being a dielectric in the first portion of the PCB, the second portion of the fourth layer being a dielectric in the second portion of the PCB, the third portion of the fourth layer being associated with power of the third portion of the PCB; and
a power filter operatively coupled to the first portion of the PCB and the second portion of the PCB.
2. The apparatus of claim 1 , wherein:
the fourth layer is disposed between the first layer and a first outer surface of the PCB, and
a fifth layer from the plurality of layers is a dielectric in the first portion of the PCB and the second portion of the PCB, the fifth layer is disposed between the second layer and a second outer surface of the PCB opposite the first outer surface of the PCB.
3. The apparatus of claim 1 , wherein:
the PCB includes a third portion mutually exclusive and physically separate from the first portion of the PCB and the second portion of the PCB,
the first layer having a third portion mutually exclusive and physically separate from the first portion of the first layer and the second portion of the first layer, the third portion of the first layer being a dielectric in the third portion of the PCB,
the second layer having a third portion mutually exclusive and physically separate from the first portion of the second layer and the second portion of the second layer, the third portion of the second layer being a dielectric in the third portion of the PCB,
the third layer having a third portion mutually exclusive and physically separate from the first portion of the third layer and the second portion of the third layer, the third portion of the third layer being a dielectric in the third portion of the PCB.
4. The apparatus of claim 1 , wherein the power filter is a first power filter, the apparatus further comprising: a second power filter operatively coupled to the second portion of the PCB and the third portion of the PCB.
5. The apparatus of claim 1 , wherein:
the first portion of PCB has a plurality of vias defining an electromagnetic interference (EMI) shield portion for the first portion of the PCB, the second portion of the PCB has a plurality of vias defining an EMI shield portion for the second portion of the PCB.
6. The apparatus of claim 1 , wherein the first portion of the PCB is configured to perform a first function and not a second function, the second portion of the PCB is configured to perform the second function and not the first function.
7. The apparatus of claim 1 , wherein the first portion of the PCB is configured to perform processing functions and not storage functions, the second portion of the PCB is configured to perform storage functions and not processing functions.
8. The apparatus of claim 1 , wherein:
a power port of the first portion of the PCB is defined by a via between the first layer and an outer surface of the PCB,
a power port of the second portion of the PCB is defined by a via between the second layer and the outer surface of the PCB,
the power filter being operatively coupled to the power port of the first portion of the PCB and the power port of the second portion of the PCB to provide power isolation between the first portion of the PCB and the second portion of the PCB.
9. The apparatus of claim 1 , wherein:
the first portion of the PCB has a plurality of vias that define at least one row of vias along an edge of the first portion of the PCB,
the second portion of the PCB has a plurality of vias define at least one row of vias along an edge of the second of the PCB,
the edge of the first portion of the PCB and the edge of the second portion of the PCB substantially abutting each other.
10. The apparatus of claim 1 , wherein the third layer continuously spans an entirety of the first portion of the PCB and the second portion of the PCB.
11. The apparatus of claim 1 , wherein:
the first portion of the PCB includes a plurality of vias at a boundary of the first portion of the PCB,
the second portion of the PCB includes a plurality of vias at a boundary of the second portion of the PCB,
the plurality of vias of the first portion of the PCB and the plurality of vias of the second portion of the PCB collectively configured to separate and isolate the first portion of the PCB and the second portion of the second PCB.
12. An apparatus, comprising:
a printed circuit board (PCB) having a plurality of layers and including a first portion and a second portion mutually exclusive from the first portion of the PCB, the first portion of PCB has a plurality of vias defining an electromagnetic interference (EMI) shield portion for the first portion of the PCB, the second portion of the PCB has a plurality of vias defining an EMI shield portion for the second portion of the PCB,
a first layer from the plurality of layers having a first portion and a second portion mutually exclusive and physically separate from the first portion of the first layer, the first portion of the first layer being associated with data of the first portion of the PCB, the second portion of the first layer being a dielectric in the second portion of the PCB,
a second layer from the plurality of layers having a first portion and a second portion mutually exclusive and physically separate from the first portion of the second layer, the first portion of the second layer being a dielectric in the first portion of the PCB, the second portion of the second layer being associated with data of the second portion of the PCB,
a third layer from the plurality of layers being a dielectric in the first portion of the PCB and the second portion of the PCB, the third layer being disposed between the first layer and the second layer; and
a data filter operatively coupled to the first portion of the PCB and the second portion of the PCB.
13. The apparatus of claim 12 , wherein:
a fourth layer from the plurality of layers is a dielectric in the first portion of the PCB and the second portion of the PCB, the fourth layer is disposed between the first layer and a first outer surface of the PCB, and
a fifth layer from the plurality of layers is a dielectric in the first portion of the PCB and the second portion of the PCB, the fifth layer is disposed between the second layer and a second outer surface of the PCB opposite the first outer surface of the PCB.
14. The apparatus of claim 12 , wherein:
the PCB includes a third portion mutually exclusive and physically separate from the first portion of the PCB and the second portion of the PCB,
the first layer having a third portion mutually exclusive and physically separate from the first portion of the first layer and the second portion of the first layer, the third portion of the first layer being a dielectric in the third portion of the PCB,
the second layer having a third portion mutually exclusive and physically separate from the first portion of the second layer and the second portion of the second layer, the third portion of the second layer being a dielectric in the third portion of the PCB,
the third layer having a third portion mutually exclusive and physically separate from the first portion of the third layer and the second portion of the third layer, the third portion of the third layer being a dielectric in the third portion of the PCB.
15. The apparatus of claim 12 , wherein:
the PCB includes a third portion mutually exclusive and physically separate from the first portion of the PCB and the second portion of the PCB,
a fourth layer from the plurality of layers having a first portion, a second portion and a third portion, the first portion of the fourth layer is mutually exclusive and physically separate from the second portion of the fourth layer and the third portion of the fourth layer, the second portion of the fourth layer is mutually exclusive and physically separate from the third portion of the fourth layer,
the first portion of the fourth layer being a dielectric in the first portion of the PCB, the second portion of the fourth layer being a dielectric in the second portion of the PCB, the third portion of the fourth layer being associated with data of the third portion of the PCB.
16. The apparatus of claim 15 , wherein the data filter is a first data filter, the apparatus further comprising:
a second data filter operatively coupled to the second portion of the PCB and the third portion of the PCB.
17. The apparatus of claim 12 , wherein the first portion of the PCB is configured to perform a first function and not a second function, the second portion of the PCB is configured to perform the second functions and not the first functions.
18. The apparatus of claim 12 , wherein the first portion of the PCB is configured to perform processing functions and not storage functions, the second portion of the PCB is configured to perform storage function and not processing function.
19. The apparatus of claim 12 , wherein:
a data port of the first portion of the PCB is defined by a via between the first layer and an outer surface of the PCB,
a data port of the second portion of the PCB is defined by a via between the second layer and the outer surface of the PCB,
the data filter being operatively coupled to the data port of the first portion of the PCB and the data port of the second portion of the PCB to prevent unintentional transfer of data between the first portion of the PCB and the second portion of the PCB.
20. The apparatus of claim 12 , wherein the data filter is included within an integrated circuit (IC) that performs data filtering and/or signal conditioning during operation of the IC, the IC having a first pin operatively coupled to a data port of the first portion of the PCB, the IC having a second pin operatively coupled to a data port of the second portion of the PCB.
21. The apparatus of claim 12 , wherein the third layer continuously spans an entirety of the first portion of the PCB and the second portion of the PCB.
22. The apparatus of claim 12 , wherein:
the plurality of vias of the first portion of the PCB at a boundary of the first portion of the PCB,
the plurality of vias of the second portion of the PCB at a boundary of the second portion of the PCB,
the plurality of vias of the first portion of the PCB and the plurality of vias of the second portion of the PCB collectively configured to separate and isolate the first portion of the PCB and the second portion of the second PCB.